PIC16F882_12 Datasheet, PDF (178/338 Pages) Microchip Technology – 28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers

PIC16F882/883/884/886/887
FIGURE 12-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
RX/DT
pin
TX/CK pin
(SCKP = 0)
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
TX/CK pin
(SCKP = 1)
Write to
bit SREN
SREN bit
CREN bit ^{‘0’}
‘0’
RCIF bit
(Interrupt)
Read
RXREG
Note:
Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
TABLE 12-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
BAUDCTL ABDOVF RCIDL
—
SCKP BRG16
—
WUE ABDEN
166
INTCON
GIE
PEIE
T0IE
INTE RBIE
T0IF
INTF
RBIF
33
PIE1
—
ADIE
RCIE
TXIE SSPIE CCP1IE TMR2IE TMR1IE
34
PIR1
—
ADIF
RCIF
TXIF SSPIF CCP1IF TMR2IF TMR1IF
36
RCREG
EUSART Receive Data Register
162
RCSTA
SPEN
RX9 SREN CREN ADDEN FERR OERR RX9D
165
SPBRG
BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0
167
SPBRGH
BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8
167
TRISC
TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
55
TXREG
EUSART Transmit Data Register
157
TXSTA
CSRC
TX9
TXEN SYNC SENDB BRGH TRMT TX9D
164
Legend: x = unknown, – = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Master
Reception.
DS41291G-page 178
 2006-2012 Microchip Technology Inc.