DSPIC33FJ06GS101A-I Datasheet, PDF (175/352 Pages) Microchip Technology – 16-Bit Microcontrollers and Digital Signal Controllers with High-Speed PWM, ADC and Comparators

dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
12.0 TIMER2 FEATURES
Note 1: This data sheet summarizes the features
of the dsPIC33FJ06GS001/101A/102A/
202A and dsPIC33FJ09GS302 families
of devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 11. “Timers”
(DS70205) in the “dsPIC33F/PIC24H
Family Reference Manual”, which is
available on the Microchip web site
(www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
Timer2 is a Type B timer with an external clock input
(TxCK) that is always synchronized to the internal
device clock and the clock synchronization is
performed after the prescaler.
The Timer2 module can operate in one of the following
modes:
• Timer mode
• Gated Timer mode
• Synchronous Counter mode
In Timer and Gated Timer modes, the input clock is
derived from the internal instruction cycle clock (FCY).
In Synchronous Counter mode, the input clock is
derived from the external clock input at the TxCK pin.
The Timer modes are determined by the following bits:
• TCS (TxCON<1>): Timer Clock Source Control bit
• TGATE (TxCON<6>): Timer Gate Control bit
The Timer control bit settings for different operating
modes are given in Table 12-1.
TABLE 12-1: TIMER MODE SETTINGS
Mode
TCS
TGATE
Timer
0
0
Gated Timer
0
1
Synchronous Counter
1
x
12.1 16-Bit Operation
To configure any of the timers for individual 16-bit
operation:
1. Select the timer prescaler ratio using the
TCKPS<1:0> bits.
2. Set the Clock and Gating modes using the TCS
and TGATE bits.
3. Load the Timer Period value into the PRx
register.
4. If interrupts are required, set the Timerx Interrupt
Enable bit, TxIE. Use the priority bits,
TxIP<2:0>, to set the interrupt priority.
5. Set the TON bit.
FIGURE 12-1:
TYPE B TIMER BLOCK DIAGRAM (x = 2)
TxCK
Gate
Sync
FP
Prescaler
(/n)
TCKPS<1:0>
Prescaler
(/n)
Sync
TCKPS<1:0>
Falling Edge
Detect
10
00
1 _{Set TxIF Flag}
0
TMRx
Reset
TGATE
x1
Equal
Comparator
TGATE
TCS
PRx
 2011-2012 Microchip Technology Inc.
DS75018C-page 175