MIC45404 Datasheet, PDF (16/32 Pages) Microchip Technology – 19V 5A Ultra-Low Profile DC-to-DC Power Module

MIC45404
4.4 Enable/Delay (EN/DLY)
The EN/DLY pin is a dual threshold pin that turns the
internal LDO on/off and starts/stops the power delivery
to the output, as shown in Figure 4-1.
V_IN
EN/DLY
Enable LDO
Comparator
EN_I
2 µA
EN_LDO_R
515 mV _{Enable Power}
Comparator
A_GND
EN_R
1.21V
Enable
150 mV _Power
Delivery
FIGURE 4-1:
EN/DLY Pin Functionality.
The threshold for LDO enable is 515 mV (typical) with
a hysteresis of approximately 30 mV. This hysteresis is
enough because at the time of LDO activation, there is
still no switching activity.
The threshold for power delivery is a precise 1.21V,
±70 mV. A 150 mV typical hysteresis prevents chattering
due to switching noise and/or slow edges.
A 2 µA typical pull-up current, with ±1 µA accuracy, per-
mits the implementation of a start-up delay by means of
an external capacitor. In this case, it is necessary to use
an open-drain driver to disable the MIC45404 while
maintaining the start-up delay function.
4.5 Power Good (PG)
The PG pin is an open-drain output that requires an
external pull-up resistor to a pull-up voltage (V_{PU_PG}),
lower than 5.5V, for being asserted to a logic HIGH
level. The PG pin is asserted with a typical delay of
0.45 ms when the output voltage (OUTSNS) reaches
92.5% of its target regulation voltage. This pin is
deasserted with a typical delay of 80 µs when the
output voltage falls below 90% of its target regulation
voltage. The PG falling delay acts as a deglitch timer
against very short spikes. The PG output is always
immediately deasserted when the EN/DLY pin is below
the power delivery enable threshold (EN_R/EN_F).
The pull-up resistor should be large enough to limit the
PG pin current to below 2 mA.
4.6 Inductor (LX, OUT) and Bootstrap
(BST) Pins
The internal inductor is connected across the LX and
OUT pins. The high-side MOSFET driver circuit is pow-
ered between BST and LX by means of an internal
capacitor that is replenished from rail V_DDP during the
low-side MOSFET on time. The bootstrap diode is
internal.
4.7 Output Sensing (OUTSNS) and
Compensation (COMP) Pins
OUTSNS should be connected exactly to the desired
Point-of-Load (POL) regulation, avoiding parasitic
resistive drops. The impedance seen into the OUTSNS
pin is high (tens of k or more, depending on the
selected output voltage value), therefore, its loading
effect is typically negligible. OUTSNS is also used by
the slope compensation generator.
The COMP pin is the connection for the external com-
pensation network. COMP is driven by the output of the
transconductance error amplifier. Care must be taken
to return the compensation network ground directly to
A_GND.
4.8 Soft Start
The MIC45404 internal reference is ramped up at a
0.42 V/ms rate. Note that this is the internal reference
soft start slew rate and that the actual slew rate seen at
the output should take into account the internal divider
attenuation, as detailed in the Section 5.0 “Application
Information”.
4.9 Switching Frequency (FREQ)
The MIC45404 features three different selectable
switching frequencies (400 kHz, 565 kHz and
790 kHz). Frequency selection is tied with a specific
output voltage selection, as described in Section 5.5
“Permissible MIC45404 Settings Combinations”.
4.10 Pre-Biased Output Start-up
The MIC45404 is designed to achieve safe start-up into
a pre-biased output without discharging the output
capacitors.
4.11 Thermal Shutdown
The MIC45404 has a thermal shutdown protection that
prevents operation at excessive temperature. The
thermal shutdown threshold is typically set at +160°C,
with a hysteresis of +25°C.
DS20005478A-page 16
 2015 Microchip Technology Inc.