MIC45404 Datasheet, PDF (15/32 Pages) Microchip Technology – 19V 5A Ultra-Low Profile DC-to-DC Power Module

4.0 FUNCTIONAL DESCRIPTION
The MIC45404 is a pin-programmable, 5A Valley
Current mode controlled power module, with an input
voltage range from 4.5V to 19V.
The MIC45404 requires a minimal amount of external
components. Only two supply decoupling capacitors
and a compensation network are external. The
flexibility in designing the external compensation
allows the user to optimize the design across the entire
input voltage and selectable output voltages range.
4.1 Theory of Operation
Valley Current mode control is a fixed frequency, lead-
ing-edge modulated Pulse-Width Modulation (PWM)
Current mode control. Differing from the Peak Current
mode, the Valley Current mode clock marks the turn-off
of the high-side switch. Upon this instant, the
MIC45404 low-side switch current level is compared
against the reference current signal from the error
amplifier. When the falling low-side switch current sig-
nal drops below the current reference signal, the
high-side switch is turned on. As a result, the inductor
valley current is regulated to a level dictated by the
output of the error amplifier.
The feedback loop includes an internal programmable
reference and output voltage sensing attenuator, thus
removing the need for external feedback components
and improving regulation accuracy. Output voltage feed-
back is achieved by connecting the OUTSNS pin directly
to the output. The high-performance transconductance
error amplifier drives an external compensation network
at the COMP pin. The COMP pin voltage represents the
reference current signal. This pin voltage is fed to the
Valley Current mode modulator, which also adds slope
compensation to ensure current loop stability.
Internal inductor, power MOSFETs and internal
bootstrap diode complete the power train.
Overcurrent protection and thermal shutdown protect
the MIC45404 from Faults or abnormal operating
conditions.
4.2 Supply Rails (V_IN, V_DDA, V_DDP)
and Internal LDO
V_IN pins represent the power train input. These pins are
the drain connection of the internal high-side MOSFET
and should be bypassed to GND, at least with a X5R or
X7R 10 µF ceramic capacitor, placed as close as
possible to the module. Multiple capacitors are
recommended.
MIC45404
An internal LDO provides a clean supply (5.1V typical)
for the analog circuits at the V_DDA pin. The internal LDO
is also powered from V_IN, as shown in the Functional
Diagram. The internal LDO is enabled when the
voltage at the EN/DLY pin exceeds about 0.51V, and
regulation takes place as soon as enough voltage has
been established between the V_IN and V_DDA pins. An
internal Undervoltage Lockout (UVLO) circuit monitors
the level of V_DDA. The V_DDA pin needs external bypass-
ing to GND by means of a 2.2 µF X5R or X7R ceramic
capacitor, placed as close as possible to the module.
V_DDP is the power supply rail for the gate drivers and
bootstrap circuit. This pin is bypassed to GND_EXT by
means of an internal high-frequency ceramic capacitor.
For this reason, the GND_EXT pins should be routed
with a low-inductance path to the GND net. An internal
10 resistor is provided between V_DDA and V_DDP,
allowing the implementation of a switching noise atten-
uation RC filter with the minimum amount of external
components. It is possible, although typically not
necessary, to lower the RC time constant by connecting
an external resistor between V_DDA and V_DDP.
If the input rail is within 4.5V to 5.5V, it is possible to
bypass the internal LDO by connecting V_IN, V_DDA and
V_DDP together. Local decoupling of the V_DDA pin is still
recommended.
4.3 Pin-Strapping Programmability
(VOSET0, VOSET1, FREQ, I_LIM)
The MIC45404 uses pin strapping to set the output volt-
age (VOSET0, VOSET1), switching frequency (FREQ)
and current limit (I_LIM). No external passives are needed,
therefore, the external component count is minimized.
Each pin is a three-state input (connect to GND for LOW
logic level, connect to V_DDA for HIGH logic level or leave
unconnected for High Z). The logic level of the pins is
read and frozen in the internal configuration logic
immediately after the V_DDA rail comes up and becomes
stabilized. After this instant, any change of the input logic
level on the pins will have no effect until the V_DDA power
is cycled again. The values corresponding to each
particular pin strapping configuration are detailed in
Section 5.0 “Application Information”.
 2015 Microchip Technology Inc.
DS20005478A-page 15