DSPIC30F6015-30I-PT Datasheet, PDF (157/236 Pages) Microchip Technology – High-Performance, 16-Bit Digital Signal Controllers

dsPIC30F6010A/6015
FIGURE 21-5:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
Internal POR
OST Time-out
TOST
PWRT Time-out
Internal Reset
21.3.1.1 POR with Long Crystal Start-up
Time (with FSCM Enabled)
The oscillator start-up circuitry is not linked to the POR
circuitry. Some crystal circuits (especially low frequency
crystals) will have a relatively long start-up time. There-
fore, one or more of the following conditions is possible
after the POR timer and the PWRT have expired:
• The oscillator circuit has not begun to oscillate.
• The Oscillator Start-up Timer has NOT expired (if
a crystal oscillator is used).
• The PLL has not achieved a LOCK (if PLL is
used).
If the FSCM is enabled and one of the above conditions
is true, then a clock failure trap will occur. The device
will automatically switch to the FRC oscillator and the
user can switch to the desired crystal oscillator in the
trap ISR.
21.3.1.2 Operating without FSCM and PWRT
If the FSCM is disabled and the Power-up Timer
(PWRT) is also disabled, then the device will exit rapidly
from Reset on power-up. If the clock source is FRC,
LPRC, EXTRC or EC, it will be active immediately.
If the FSCM is disabled and the system clock has not
started, the device will be in a frozen state at the Reset
vector until the system clock starts. From the user’s
perspective, the device will appear to be in Reset until
a system clock is available.
TPWRT
21.3.2 BOR: PROGRAMMABLE
BROWN-OUT RESET
The BOR (Brown-out Reset) module is based on an
internal voltage reference circuit. The main purpose of
the BOR module is to generate a device Reset when a
brown-out condition occurs. Brown-out conditions are
generally caused by glitches on the AC mains (i.e.,
missing portions of the AC cycle waveform due to bad
power transmission lines or voltage sags due to exces-
sive current draw when a large inductive load is turned
on).
The BOR module allows selection of one of the
following voltage trip points:
• 2.6V–2.71V
• 4.1V–4.4V
• 4.58V–4.73V
Note:
The BOR voltage trip points indicated here
are nominal values provided for design
guidance only.
A BOR will generate a Reset pulse which will reset the
device. The BOR will select the clock source, based on
the device Configuration bit values (FOS<2:0> and
FPR<4:0>). Furthermore, if an oscillator mode is
selected, the BOR will activate the Oscillator Start-up
Timer (OST). The system clock is held until OST
expires. If the PLL is used, then the clock will be held
until the LOCK bit (OSCCON<5>) is ‘1’.
© 2006 Microchip Technology Inc.
DS70150B-page 155