DSPIC30F6015-30I-PT Datasheet, PDF (144/236 Pages) Microchip Technology – High-Performance, 16-Bit Digital Signal Controllers

dsPIC30F6010A/6015
20.8 A/D Acquisition Requirements
The analog input model of the 10-bit A/D converter is
shown in Figure 20-3. The total sampling time for the
A/D is a function of the internal amplifier settling time,
device VDD and the holding capacitor charge time.
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the voltage level on the analog input
pin. The analog output source impedance (RS), the
interconnect impedance (RIC), and the internal sam-
pling switch (RSS) impedance combine to directly affect
the time required to charge the capacitor CHOLD. The
combined impedance must therefore be small enough
to fully charge the holding capacitor within the chosen
sample time. To minimize the effects of pin leakage
currents on the accuracy of the A/D converter, the max-
imum recommended source impedance, RS, is 5 kΩ for
conversion rates up to 500 ksps and a maximum of
500Ω for conversion rates up to 1 Msps. After the
analog input channel is selected (changed), this sam-
pling function must be completed prior to starting the
conversion. The internal holding capacitor will be in a
discharged state prior to each sample operation.
The user must allow at least 1 TAD period of sampling
time, TSAMP, between conversions to allow each sam-
ple to be acquired. This sample time may be controlled
manually in software by setting/clearing the SAMP bit,
or it may be automatically controlled by the A/D con-
verter. In an automatic configuration, the user must
allow enough time between conversion triggers so that
the minimum sample time can be satisfied. Refer to
Section 24.0 “Electrical Characteristics” for TAD and
sample time requirements.
FIGURE 20-3:
A/D CONVERTER ANALOG INPUT MODEL
Rs ^ANx
VA
CPIN
VDD
VT = 0.6V
VT = 0.6V
RIC ≤ 250Ω
I leakage
± 500 nA
Sampling
Switch
RSS
RSS ≤ 3 kΩ
CHOLD
= DAC capacitance
= 4.4 pF
VSS
Legend: CPIN
= input capacitance
VT
= threshold voltage
I leakage = leakage current at the pin due to
various junctions
RIC
= interconnect resistance
RSS
= sampling switch resistance
CHOLD = sample/hold capacitance (from DAC)
Note: CPIN value depends on device package and is not tested. Effect of CPIN negligible if Rs ≤ 5 kΩ.
DS70150B-page 142
© 2006 Microchip Technology Inc.