DSPIC30F4013-20I Datasheet, PDF (132/220 Pages) Microchip Technology – High-Performance, 16-Bit Digital Signal Controllers

dsPIC30F3014/4013
FIGURE 19-3:
ADCLK
CONVERTING 1 CHANNEL AT 200 KSPS, AUTO-SAMPLE START, 1 TAD
SAMPLING TIME
TSAMP
= 1 TAD
TSAMP
= 1 TAD
TCONV
= 14 TAD
TCONV
= 14 TAD
SAMP
DONE
ADCBUF0
ADCBUF1
Instruction Execution BSET ADCON1, ASAM
19.8 A/D Acquisition Requirements
The analog input model of the 12-bit A/D converter is
shown in Figure 19-4. The total sampling time for the A/
D is a function of the internal amplifier settling time and
the holding capacitor charge time.
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the voltage level on the analog input
pin. The source impedance (RS), the interconnect
impedance (RIC), and the internal sampling switch
(RSS) impedance combine to directly affect the time
required to charge the capacitor CHOLD. The combined
impedance of the analog sources must therefore be
small enough to fully charge the holding capacitor
within the chosen sample time. To minimize the effects
of pin leakage currents on the accuracy of the A/D con-
verter, the maximum recommended source imped-
ance, RS, is 2.5 kΩ. After the analog input channel is
selected (changed), this sampling function must be
completed prior to starting the conversion. The internal
holding capacitor will be in a discharged state prior to
each sample operation.
FIGURE 19-4:
12-BIT A/D CONVERTER ANALOG INPUT MODEL
Rs ^ANx
VA
CPIN
VDD
VT = 0.6V
VT = 0.6V
RIC ≤ 250Ω
I leakage
± 500 nA
Sampling
Switch
RSS
RSS ≤ 3 kΩ
CHOLD
= DAC capacitance
= 18 pF
VSS
Legend: CPIN
= input capacitance
VT
= threshold voltage
I leakage = leakage current at the pin due to
various junctions
RIC
= interconnect resistance
RSS
= sampling switch resistance
CHOLD = sample/hold capacitance (from DAC)
Note: CPIN value depends on device package and is not tested. Effect of CPIN negligible if Rs ≤ 2.5 kΩ.
DS70138E-page 130
© 2007 Microchip Technology Inc.