DSPIC30F4013-20I Datasheet, PDF (101/220 Pages) Microchip Technology – High-Performance, 16-Bit Digital Signal Controllers

16.2 Enabling and Setting Up UART
16.2.1 ENABLING THE UART
The UART module is enabled by setting the UARTEN
bit in the UxMODE register (where x = 1 or 2). Once
enabled, the UxTX and UxRX pins are configured as an
output and an input, respectively, overriding the TRIS
and LAT register bit settings for the corresponding I/O
port pins. The UxTX pin is at logic ‘1’ when no
transmission is taking place.
16.2.2 DISABLING THE UART
The UART module is disabled by clearing the UARTEN
bit in the UxMODE register. This is the default state
after any Reset. If the UART is disabled, all I/O pins
operate as port pins under the control of the LAT and
TRIS bits of the corresponding port pins.
Disabling the UART module resets the buffers to empty
states. Any data characters in the buffers are lost and
the baud rate counter is reset.
All error and status flags associated with the UART
module are reset when the module is disabled. The
URXDA, OERR, FERR, PERR, UTXEN, UTXBRK and
UTXBF bits are cleared, whereas RIDLE and TRMT
are set. Other control bits, including ADDEN,
URXISEL<1:0>, UTXISEL, as well as the UxMODE
and UxBRG registers, are not affected.
Clearing the UARTEN bit while the UART is active
aborts all pending transmissions and receptions and
resets the module, as defined above. Re-enabling the
UART restarts the UART in the same configuration.
16.2.3 ALTERNATE I/O
The alternate I/O function is enabled by setting the
ALTIO bit (UxMODE<10>). If ALTIO = 1, the UxATX
and UxARX pins (alternate transmit and alternate
receive pins, respectively) are used by the UART mod-
ule instead of the UxTX and UxRX pins. If ALTIO = 0,
the UxTX and UxRX pins are used by the UART
module.
16.2.4 SETTING UP DATA, PARITY AND
STOP BIT SELECTIONS
Control bits PDSEL<1:0> in the UxMODE register are
used to select the data length and parity used in the
transmission. The data length may either be 8 bits with
even, odd or no parity, or 9 bits with no parity.
The STSEL bit determines whether one or two Stop bits
are used during data transmission.
The default (power-on) setting of the UART is 8 bits, no
parity and 1 Stop bit (typically represented as 8, N, 1).
dsPIC30F3014/4013
16.3 Transmitting Data
16.3.1 TRANSMITTING IN 8-BIT DATA
MODE
The following steps must be performed in order to
transmit 8-bit data:
1. Set up the UART:
First, the data length, parity and number of Stop
bits must be selected. Then, the transmit and
receive interrupt enable and priority bits are
setup in the UxMODE and UxSTA registers.
Also, the appropriate baud rate value must be
written to the UxBRG register.
2. Enable the UART by setting the UARTEN bit
(UxMODE<15>).
3. Set the UTXEN bit (UxSTA<10>), thereby
enabling a transmission.
4. Write the byte to be transmitted to the lower byte
of UxTXREG. The value is transferred to the
Transmit Shift register (UxTSR) immediately,
and the serial bit stream starts shifting out during
the next rising edge of the baud clock. Alterna-
tively, the data byte can be written while UTXEN
= 0, following which, the user can set UTXEN.
This causes the serial bit stream to begin imme-
diately because the baud clock starts from a
cleared state.
5. A transmit interrupt is generated, depending on
the value of the interrupt control bit UTXISEL
(UxSTA<15>).
16.3.2 TRANSMITTING IN 9-BIT DATA
MODE
The sequence of steps involved in the transmission of
9-bit data is similar to 8-bit transmission, except that a
16-bit data word (of which the upper 7 bits are always
clear) must be written to the UxTXREG register.
16.3.3 TRANSMIT BUFFER (UXTXB)
The transmit buffer is 9 bits wide and 4 characters
deep. Including the Transmit Shift register (UxTSR),
the user effectively has a 5-deep FIFO (First-In, First-
Out) buffer. The UTXBF Status bit (UxSTA<9>)
indicates whether the transmit buffer is full.
If a user attempts to write to a full buffer, the new data
is not accepted into the FIFO, and no data shift occurs
within the buffer. This enables recovery from a buffer
overrun condition.
The FIFO is reset during any device Reset but is not
affected when the device enters or wakes up from a
Power-Saving mode.
© 2007 Microchip Technology Inc.
DS70138E-page 99