PL138-48 Datasheet, PDF (11/20 Pages) Microchip Technology – 2.5V to 3.3V, Low-Skew, 1:4 Differential PECL Fanout Buffer

PL138-48
FIGURE 5-8:
CLK-IN Input Driven by a
Single-Ended LVPECL.
FIGURE 5-9:
HCSL Driver.
CLK-IN Input Driven by an
HCSL presents its signals very close to the ground rail,
below the V_CMR range, so the HCSL signals cannot be
connected to the PL138 input directly. AC-coupling is
required for HCSL signals on the PL138 input.
TABLE 5-2:
INPUT CLOCK CONTROL
SELECTION
CLK_SEL
Selected Source
0
CLK-IN0
1
CLK-IN1
TABLE 5-3: INPUT CLOCK FUNCTION
Inputs
Outputs
CLK-EN CLKSEL Source Q0:Q3 Q0B:Q3B
0
0
CLK-IN0 Disabled Disabled
Low
High
0
1
CLK-IN1 Disabled Disabled
Low
High
1
0
CLK-IN0 Enabled Enabled
1
1
CLK-IN1 Enabled Enabled
5.2 Termination for LVPECL Outputs
The required termination for LVPECL is 50Ω to a
V_CC-2V DC voltage level. Below are two schematics to
implement this termination.
FIGURE 5-10:
Input Logic Block Diagram.
TABLE 5-1:
INPUT PIN
CHARACTERISTICS
Input Parameter Min. Typ. Max. Units
CLK-IN0, Pull-Down — 75 —
CLK-IN1 Resistor
CLK-IN0B, Pull-Up & — 100 —
CLK_IN1B Pull-Down
Resistors
kΩ
CLK-EN Pull-Up — 50 —
Resistor
CLKSEL Pull-Down — 50 —
Resistor
FIGURE 5-11:
Schematic #1.
LVPECL Termination
• V_CC = 3.3V
- Ideal values: R1 = 127Ω, R2 = 82.5Ω
- Commercial values (E24): R1 = 130Ω,
R2 = 82Ω
• V_CC = 2.5V
- Ideal values: R1 = 250Ω, R2 = 62.5Ω
- Commercial values (E24): R1 = 240Ω,
R2 = 62Ω
 2016 Microchip Technology Inc.
DS20005543B-page 11