PL138-48 Datasheet, PDF (10/20 Pages) Microchip Technology – 2.5V to 3.3V, Low-Skew, 1:4 Differential PECL Fanout Buffer

PL138-48
5.0 APPLICATION INFORMATION
5.1 Input Logic Configurations
The following circuits show different configurations for different input logic type signals. For good signal integrity at the
PL138 input, the signals need to be properly terminated according to the logic type requirements. The signals need to
be presented at the PL138 input according to V_CMR, V_PP, and other input requirements.
FIGURE 5-1:
CLK-IN Input Driven by a
3.3V LVPECL Driver.
FIGURE 5-5:
LVDS Driver.
CLK-IN Input Driven by an
FIGURE 5-2:
3.3V LVPECL Driver,
Alternative Termination.
FIGURE 5-6:
AC-Coupling.
LVDS Driver, Alternative
This circuit is for compatibility only. AC-coupling is not
really required for LVDS. The V_CMR range of the PL138
reaches low enough that LVDS signals can be
connected directly to the PL138 input like in the circuit
in Figure 5-5.
FIGURE 5-3:
CML Driver.
CLK-IN Input Driven by a
FIGURE 5-7:
CMOS Driver.
CLK-IN Input Driven by a
FIGURE 5-4:
SSTL Driver.
CLK-IN Input Driven by an
DS20005543B-page 10
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