PIC16LF145X Datasheet, PDF (11/38 Pages) Microchip Technology – PIC16(L)F145X Memory Programming Specification

4.0 PROGRAM/VERIFY MODE
In Program/Verify mode, the program memory and the
configuration memory can be accessed and
programmed in serial fashion. ICSPDAT and
ICSPCLK are used for the data and the clock,
respectively. All commands and data words are
transmitted LSb first. Data changes on the rising edge
of the ICSPCLK and latched on the falling edge. In
Program/Verify mode both the ICSPDAT and
ICSPCLK are Schmitt Trigger inputs. The sequence
that enters the device into Program/Verify mode
places all other logic into the Reset state. Upon
entering Program/Verify mode, all I/Os are
automatically configured as high-impedance inputs
and the address is cleared.
4.1 High-Voltage Program/Verify Mode
Entry and Exit
There are two different methods of entering Program/
Verify mode via high-voltage:
• VPP – First entry mode
• VDD – First entry mode
4.1.1 VPP – FIRST ENTRY MODE
To enter Program/Verify mode via the VPP-first method
the following sequence must be followed:
1. Hold ICSPCLK and ICSPDAT low. All other pins
should be unpowered.
2. Raise the voltage on MCLR from 0V to VIHH.
3. Raise the voltage on VDD from 0V to the desired
operating voltage.
The VPP-first entry prevents the device from executing
code prior to entering Program/Verify mode. For
example, the device will execute code when
Configuration Word 1 has MCLR disabled (MCLRE =
0), the Power-up Timer is disabled (PWRTE = 0), the
internal oscillator is selected (FOSC = 100), and
ICSPCLK and ICSPDAT pins are driven by the user
application. Since this may prevent entry, VPP-first
Entry mode is strongly recommended. See the timing
diagram in Figure 8-2.
PIC16(L)F145X
4.1.2 VDD – FIRST ENTRY MODE
To enter Program/Verify mode via the VDD-first method
the following sequence must be followed:
1. Hold ICSPCLK and ICSPDAT low.
2. Raise the voltage on VDD from 0V to the desired
operating voltage.
3. Raise the voltage on MCLR from VDD or below
to VIHH.
The VDD-first method is useful when programming the
device when VDD is already applied, for it is not
necessary to disconnect VDD to enter Program/Verify
mode. See the timing diagram in Figure 8-1.
4.1.3 PROGRAM/VERIFY MODE EXIT
To exit Program/Verify mode take MCLR to VDD or
lower (VIL). See Figures 8-3 and 8-4.
4.2 Low-Voltage Programming (LVP)
Mode
The Low-Voltage Programming mode allows devices to
be programmed using VDD only, without high voltage.
When the LVP bit of Configuration Word 2 register is
set to ‘1’, the low-voltage ICSP programming entry is
enabled. To disable the Low-Voltage ICSP mode, the
LVP bit must be programmed to ‘0’. This can only be
done while in the High-Voltage Entry mode.
Entry into the Low-Voltage ICSP Program/Verify modes
requires the following steps:
1. MCLR is brought to VIL.
2. A 32-bit key sequence is presented on
ICSPDAT, while clocking ICSPCLK.
The key sequence is a specific 32-bit pattern, '0100
1101 0100 0011 0100 1000 0101 0000' (more
easily remembered as MCHP in ASCII). The device will
enter Program/Verify mode only if the sequence is
valid. The Least Significant bit (LSb) of the Least
Significant nibble must be shifted in first.
Once the key sequence is complete, MCLR must be
held at VIL for as long as Program/Verify mode is to be
maintained.
For low-voltage programming timing, see Figure 8-8
and Figure 8-9.
Exiting Program/Verify mode is done by no longer
driving MCLR to VIL. See Figure 8-8 and Figure 8-9.
Note:
To enter LVP mode, the LSB of the Least
Significant nibble must be shifted in first.
This differs from entering the key
sequence on other parts.
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