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PIC16LF145X Datasheet, PDF (10/38 Pages) Microchip Technology – PIC16(L)F145X Memory Programming Specification
PIC16(L)F145X
REGISTER 3-4:
CONFIGURATION WORD 2
R/P-1
R/P-1
LVP
DEBUG
bit 13
R/P-1
LPBOR
R/P-1
BORV
R/P-1
STVREN
R/P-1
PLLEN
bit 8
R/P-1
R/P-1
R/P-1
R/P-1
U-1
PLLMULT USBLSCLK
CPUDIV<1:0>
—
bit 7
U-1
R/P-1
R/P-1
—
WRT<1:0>
bit 0
Legend:
R = Readable bit
-n = Value after Bulk Erase
P = Programmable Bit
‘1’ = Bit is set
U = Unimplemented bit
‘0’ = Bit is cleared
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5-4
bit 3-2
bit 1-0
LVP: Low-Voltage Programming Enable bit(1), (2)
1 = Low-voltage programming enabled
0 = HV on MCLR/VPP must be used for programming
DEBUG: Debugger mode bit
1 = In-circuit debugger disabled, ICSPCLK and ICSPDAT pins are general purpose I/O pins
0 = In-circuit debugger enabled, ICSPCLK and ICSPDAT pins are dedicated to the debugger
LPBOR: Low-Power BOR bit
1 = Low-Power BOR is disabled
0 = Low-Power BOR is enabled
BORV: Brown-out Reset Voltage Selection bit
1 = Brown-out Reset Voltage (VBOR), low trip point selected
0 = Brown-out Reset Voltage (VBOR), high trip point selected
STVREN: Stack Overflow/Underflow Reset Enable bit
1 = Stack Overflow or Underflow will cause a Reset
0 = Stack Overflow or Underflow will not cause a Reset
PLLEN: PLLEN Enable bit
1 = PLL enabled
0 = PLL disabled
PLLMULT: PLL Multiplier Selection bit
1 = 3x PLL Output Frequency is selected
0 = 4x PLL Output Frequency is selected
USBLSCLK: USB Low-Speed Clock Selection bit
1 = USB Clock divide-by 8, (48 MHz System input clock expected)
0 = USB Clock divide-by 4, (24 MHz System input clock expected)
CPUDIV<1:0>: CPU System Clock Selection bits
11 = CPU system clock divided by 6
10 = CPU system clock divided by 3
01 = CPU system clock divided by 2
00 = No CPU system clock divide.
Unimplemented: Read as ‘1’
WRT<1:0>: Flash Memory Self-Write Protection bits
8 kW Flash memory (PIC16(L)F1454/1455/1459):
11 = Write protection off
10 = 0000h to 01FFh write-protected, 0200h to 1FFFh may be modified by PMCON control
01 = 0000h to 0FFFh write-protected, 1000h to 1FFFh may be modified by PMCON control
00 = 0000h to 1FFFh write-protected, no addresses may be modified by PMCON control
Note 1: The LVP bit cannot be programmed to ‘0’ when Programming mode is entered via LVP.
2: When LVP = 1, the ICSP™ functions are enabled on the ICSPDAT/D+/RA0 and ICSPCLK/D-/RA1 pins.
DS41620C-page 10
Advance Information
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