24AA52_05 Datasheet, PDF (11/28 Pages) Microchip Technology – 2K 2.2V I2C™ Serial EEPROM with Software Write-Protect

24AA52/24LCS52
7.0 READ OPERATION
Read operations are initiated in the same way as write
operations, with the exception that the R/W bit of the
slave address is set to ‘1’. There are three basic types
of read operations: current address read, random read
and sequential read.
7.1 Current Address Read
The 24XXX52 contains an address counter that
maintains the address of the last word accessed, inter-
nally incremented by ‘1’. Therefore, if the previous
access (either a read or write operation) was to
address n, the next current address read operation
would access data from address n+1. Upon receipt of
the slave address with R/W bit set to ‘1’, the 24XXX52
issues an acknowledge and transmits the 8-bit data
word. The master will not acknowledge the transfer, but
does generate a Stop condition and the 24XXX52
discontinues transmission (Figure 7-1).
7.2 Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, the word address must first
be set. This is done by sending the word address to the
24XXX52 as part of a write operation. Once the word
address is sent, the master generates a Start condition
following the acknowledge. This terminates the write
operation, but not before the internal Address Pointer is
set. The master then issues the control byte again, but
with the R/W bit set to a ‘1’. The 24XXX52 then issues
an acknowledge and transmits the 8-bit data word. The
master will not acknowledge the transfer, but does
generate a Stop condition and the 24XXX52
discontinues transmission (Figure 7-2).
FIGURE 7-1:
CURRENT ADDRESS READ
S
Bus Activity
T
Master
A
R
T
Control
Byte
SDA Line
S
Bus Activity
7.3 Sequential Read
Sequential reads are initiated in the same way as a
random read, with the exception that after the 24XXX52
transmits the first data byte, the master issues an
acknowledge, as opposed to a Stop condition in a
random read. This directs the 24XXX52 to transmit the
next sequentially addressed 8-bit word (Figure 7-3).
To provide sequential reads, the 24XXX52 contains an
internal Address Pointer, which is incremented by one
at the completion of each operation. This Address
Pointer allows the entire memory contents to be serially
read during one operation.
7.4 Contiguous Addressing Across
Multiple Devices
The Chip Select bits (A2, A1, A0) can be used to
expand the contiguous address space for up to 16K bits
by adding up to eight 24XXX52 devices on the same
bus. In this case, software can use A0 of the control
byte as address bit A8; A1 as address bit A9, and A2
as address bit A10. It is not possible to sequentially
read across device boundaries.
7.5 Noise Protection and Brown-Out
The 24XXX52 employs a VCC threshold detector circuit
which disables the internal erase/write logic if the VCC
is below 1.5V at nominal conditions.
The SCL and SDA inputs have Schmitt Trigger and
filter circuits which suppress noise spikes to assure
proper device operation, even on a noisy bus.
Data (n)
A
C
K
S
T
O
P
P
N
O
A
C
K
© 2005 Microchip Technology Inc.
DS21166J-page 11