MIC4605 Datasheet, PDF (9/25 Pages) Micrel Semiconductor – 85V Half-Bridge MOSFET Drivers

Micrel, Inc.
MIC4605
Timing Diagrams (Continued)
PWM signal applied to the MIC4605-2 going low causes
HO to go low typically 35ns (t_HOOFF) after the PWM input
goes low, at which point the switch node HS falls (1 − 2).
When HS reaches 2.2V (V_SWTH), the external high-side
MOSFET is deemed off and LO goes high, typically within
35ns (t_LOON). HS falling below 1.9V sets a latch that can
only be reset by PWM going high. This design prevents
ringing on HS from causing an indeterminate LO state.
Should HS never trip the aforementioned internal
comparator reference (2.2V), a falling PWM edge delayed
by 250ns will set “HS latch” allowing LO to go high. An
80ns delay gated by PWM going low may determine the
time to LO going high for fast falling HS designs (3 − 4).
PWM goes high forcing LO low in typically 35ns (t_LOOFF)
(5 − 6).
When LO reaches 1.9V (V_LOOFF), the low-side MOSFET is
deemed off and HO is allowed to go high. The delay
between these two points is typically 35ns (t_LOON). HO
goes high with a high signal on HI after a typical delay of
35ns (t_HPLH). HI going low drives HO low also with a typical
delay of 35ns (t_HPHL) (7 − 8).
HO and LO output rise and fall times (t_R/t_F) are typically
20ns driving 1000pF capacitive loads.
Note: All propagation delays are measured from the 50%
voltage level.
November 11, 2013
Figure 3. PWM Mode (MIC4605-2)
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Revision 1.0