MIC4605 Datasheet, PDF (10/25 Pages) Micrel Semiconductor – 85V Half-Bridge MOSFET Drivers

Micrel, Inc.
MIC4605
Block Diagram
For HO to be high, HI must be high and LO must be low.
HO going high is delayed by LO falling below 1.9V. The HI
and LI inputs must not rise at the same time to prevent a
glitch from occurring on the output. A minimum 50ns delay
between both inputs is recommended.
LO is turned off very quickly on the LI falling edge. LO
going high is delayed by the longer of 35ns delay of HO
control signal going “off” or the RS latch being set.
The latch is set by the quicker of either the falling edge of
HS or LI gated delay of 240ns. The latch is present to
lockout LO bounce due to ringing on HS. If HS never
adequately falls due to the absence of or the presence of a
very weak external pull-down on HS, the gated delay of
240ns at LI will set the latch allowing LO to transition high.
This in turn allows the LI startup pulse to charge the
bootstrap capacitor if the load inductor current is very low
and HS is uncontrolled. The latch is reset by the LI falling
edge.
MIC4605 Top Level Block Diagram
MIC4605-1 Cross-Conduction Lockout/PWM Input Logic Block Diagram
November 11, 2013
10
Revision 1.0