MIC25400 Datasheet, PDF (9/27 Pages) Micrel Semiconductor – 2A Dual Output PWM Synchronous Buck Regulator IC

Micrel, Inc.
Functional Description
The MIC25400 is a dual output, synchronous buck
regulators. Output regulation is performed using a fixed
frequency, voltage mode control scheme. The fixed
frequency clock drives the two sections 180° out of
phase, which reduces input ripple current.
Oscillator
An internal oscillator provides a clock signal to each of
the two sides. The clock signals are 180° out of phase
with the other. Each phase is used to generate a ramp
for the PWM comparator and a clock pulse that
terminates the switching cycle. The MIC25400 oscillator
frequency is nominally 1MHz.
UVLO
The UVLO monitors voltage on the V_IN pin. The circuit
controls both regulators (side 1 and side 2). It disables
the output drivers and discharges the EN/DLY capacitor
when V_IN is below the UVLO threshold. As V_IN rises
above the threshold, the internal high-side FET drivers
and external low-side drives are enabled and the
EN/DLY pins are released.
A low impedance source should be used to supply input
voltage to the MIC25400. When V_IN drops below the
UVLO threshold and the outputs turn off, the change in
input current will cause V_IN to slight rise. The output
voltage will momentarily turn back on if the rise in V_IN is
greater than the UVLO hysteresis.
The preferred method is to use the EN/DLY pins, as
shown in Figure 1, for startup and shutdown of the
outputs. This avoids the possibility of glitching during
startup and shutdown. If an external control signal is not
available, the circuit in Figure 1A may be used to set a
higher turn-on and turn-off threshold than the internal
UVLO circuit. Moreover, the hysteresis is adjustable and
can accommodate a wider input source impedance
range. Please refer to the MIC841 datasheet for
additional information on selecting the resistor values.
Regulator/Reference
The internal regulator generates a PVDD pin voltage that
powers the high-side MOSFET and low-side gate drive
circuits. It also generates an internal analog voltage,
A_VDD, which is used by the low level analog and digital
sections. The A_VDD voltage is also used by the bandgap
to generate a nominal 700mV for the error amplifier
reference. The output undervoltage and power good
circuits use the bandgap for their references.
The dropout of the internal regulator causes V_PVDD to
drop when V_IN is below 6V. When operating below 6V,
the PVDD pin must be jumpered to V_IN. This bypasses
the internal LDO and prevents V_PVDD from dropping out.
MIC25400
A 1µF ceramic capacitor should be used to decouple
V_PVDD-to-ground.
EN/DLY pin
The EN/DLY pins are used to turn on, turn off and soft-
start the outputs. The pins can be controlled with an
open collector or open drain device as shown in Figure
1. It must not be actively driven high or damage will
result. When disabling the output with an external
device, the enable pin turn-off time must be less than
1µs.
Figure 1. Enable and soft-start circuit
Figure 1A. Adjustable UVLO startup circuit
Minimum Output Load when Disabled
When one output is disabled and the other enabled, then
the disabled output requires a minimum output load to
prevent its output voltage from rising. Typically, a 2kΩ
load on the output will keep the output voltage below
100mV. The output setting voltage divider resistors may
be used for the 2kΩ load if the total resistance is set low
enough. A separate output resistor should be used for
lower output voltages since the voltage divider
resistance becomes impractically low.
January 2011
9
M9999-020111-C