MIC25400 Datasheet, PDF (10/27 Pages) Micrel Semiconductor – 2A Dual Output PWM Synchronous Buck Regulator IC

Micrel, Inc.
Soft-start
Enable and soft-start waveforms are shown in Figure 2.
MIC25400
Output Sequencing
Sequencing of the outputs is shown in Figure 3. The
power good pin is used to disable V_OUT2 until the V_OUT1
reaches regulation. Sequencing waveforms are shown in
Figure 4.
Figure 2. Soft-start Timing Diagram
A capacitor, C_SS, is connected to the EN/DLY pin. The
C_SS capacitor range is 4.7nf to 22nf. Releasing the pin
allows an internal current source to charge the capacitor.
The delay between the EN/DLY pin release and when
V_OUT starts to rise can be calculated by the equation
below.
t_D
=
C _SS
× V_{Threshold_Start}
I_SS
Where:
C_SS is the soft-start capacitor.
I_SS is the internal soft-start current (200µA nominal).
V_{Threshold_start} is the EN/DLY pin voltage where the output
starts to rise (1.35V nominal).
The output voltage starts to rise when voltage on the
EN/DLY pin reaches the start threshold. The output
voltage reaches regulation when the EN/DLY pin voltage
reaches the end threshold. The output voltage rise time
can be calculated by the equation below:
t_D
=
C _SS
× (V_{Threshold_End}
I_SS
− V_{Threshold_Start} )
Where:
V_{Threshold_End} is the EN/DLY pin voltage where the output
reaches regulation.
Power Good
Power good is an open drain signal that asserts when
V_OUT exceed the power good threshold. The circuit
monitors the FB pin. The internal FET is turned on while
the FB voltage is below the FB threshold. When voltage
on the FB in exceeds the FB threshold, the FET is
turned off. A pull-up resistor can be connected to P_VDD or
and external source. The external source voltage must
not exceed the maximum rating of the pin. The PG pin
can be connected to another regulator’s EN/DLY pin for
sequencing of the outputs. A pull-up resistor is not used
when the power good pin is connected to another
regulators EN/DLY pin.
Figure 3. Output Sequencing
Figure 4. Output Sequencing Waveforms
The MIC25400 must start up without a pre-biased output
voltage. During start up, the MIC25400 pulls the output
to ground if it is above 0V. This may cause the output to
ring below ground and excessive voltage on the VSW
node. A pre-bias condition can occur if the output is
turned off then immediately turned back on before the
output capacitor is discharged to ground. It is also
possible that the output of the MIC25400 could be pulled
up or pre-biased through parasitic conduction paths from
one supply rail to another in multiple voltage level ICs
like a FPGA.
January 2011
10
M9999-020111-C