KSZ8842MQL Datasheet, PDF (89/141 Pages) Micrel Semiconductor – 2-Port Ethernet Switch with Non-PCI Interface

Micrel, Inc.
KSZ8842-16/32 MQL/MVL/MVLI/MBL
Bank 45 PHY 1 MII-Register Basic Control Register (0x00): P1MBCR
This register contains Media Independent Interface (MII) register for switch port 1 as defined in the IEEE 802.3
specification.
Bit
Default
15
0
14
0
13
0
12
1
11
0
10
0
9
0
8
0
7
0
6
0
5
1
4
0
3
0
2
0
1
0
0
0
R/W Description
RO Soft reset
Not supported.
RW Far-End Loopback
1 = perform loopback as follows:
Start: RXP2/RXM2 (port 2)
Loop back: PMD/PMA of port 1’s PHY
End: TXP2/TXM2 (port 2)
0 = normal operation.
RW Force 100
1 = force 100Mbps if AN is disabled (bit 12)
0 = force 10Mbps if AN is disabled (bit 12)
RW AN Enable
1 = auto-negotiation enabled.
0 = auto-negotiation disabled.
RW Power-Down
1 = power-down.
0 = normal operation.
RO Isolate
Not supported.
RW Restart AN
1 = restart auto-negotiation.
0 = normal operation.
RW Force Full Duplex
1 = force full duplex.
0 = force half duplex.
if AN is disabled (bit 12) or AN is enabled but
failed.
RO Collision test
Not supported.
RO Reserved.
R/W HP_mdix
1 = HP Auto MDI-X mode.
0 = Micrel Auto MDI-X mode.
RW Force MDI-X
1 = force MDI-X.
0 = normal operation.
RW Disable MDI-X
1 = disable auto MDI-X.
0 = normal operation.
RW Reserved
RW Disable Transmit
1 = disable transmit.
0 = normal operation.
RW Disable LED
1 = disable LED.
0 = normal operation.
Bit is same as:
Bank 49 0x02 bit 8
Bank 49 0x02 bit 6
Bank 49 0x02 bit 7
Bank 49 0x02 bit 11
Bank 49 0x02 bit 13
Bank 49 0x02 bit 5
Bank 49 0x04 bit 15
Bank 49 0x02 bit 9
Bank 49 0x02 bit 10
Bank 49 0x02 bit 12
Bank 49 0x02 bit 14
Bank 49 0x02 bit 15
October 2007
89
M9999-102207-1.9