KSZ8842MQL Datasheet, PDF (66/141 Pages) Micrel Semiconductor – 2-Port Ethernet Switch with Non-PCI Interface

Micrel, Inc.
KSZ8842-16/32 MQL/MVL/MVLI/MBL
Bit
Default Value R/W Description
6
0x0
RW RXME Receive Multicast Enable
When this bit is set, the RX module receives all the multicast frames (including
broadcast frames).
5
0x0
RW RXUE Receive Unicast
When this bit is set, the RX module receives unicast frames that match the 48-bit
Station MAC address of the module.
4
0x0
RW RXRA Receive All
When this bit is set, the KSZ8842M receives all incoming frames, regardless of the
frame’s destination address.
3
0x0
RW RXSCE Receive Strip CRC
When this bit is set, the KSZ8842M strips the CRC on the received frames. Once
cleared, the CRC is stored in memory following the packet.
2
0x0
RW QMU Receive Multicast Hash-Table Enable
When this bit is set, this bit enables the RX function to receive multicast frames that
pass the CRC Hash filtering mechanism.
1
-
RO Reserved
0
0x0
RW RXE Receive Enable
When this bit is set, the RX block is enabled and placed in a running state. When
reset, the receive process is placed in the stopped state upon completing reception of
the current frame.
Bank 16 TXQ Memory Information Register (0x08): TXMIR
This register indicates the amount of free memory available in the TXQ of the QMU module.
Bit
15-13
12-0
Default Value R/W
-
RO
-
RO
Description
Reserved
TXMA Transmit Memory Available
The amount of memory available is represented in units of byte. The TXQ memory is
used for both frame payload, control word. There is total 4096 bytes in TXQ.
Note: Software must be written to ensure that there is enough memory for the next
transmit frame including control information before transmit data is written to the TXQ.
Bank 16 RXQ Memory Information Register (0x0A): RXMIR
This register indicates the amount of receive data available in the RXQ of the QMU module.
Bit
15-13
12-0
Default Value R/W
-
RO
-
RO
Description
Reserved
RXMA Receive Packet Data Available
The amount of Receive packet data available is represented in units of byte. The RXQ
memory is used for both frame payload, status word. There is total 4096 bytes in RXQ.
This counter will update after a complete packet is received and also issues an
interrupt when receive interrupt enable IER[13] in Bank 18 is set.
Note: Software must be written to empty the RXQ memory to allow for the new RX
frame. If this is not done, the frame may be discarded as a result of insufficient RXQ
memory.
October 2007
66
M9999-102207-1.9