KSZ8842MQL Datasheet, PDF (41/141 Pages) Micrel Semiconductor – 2-Port Ethernet Switch with Non-PCI Interface

Micrel, Inc.
KSZ8842-16/32 MQL/MVL/MVLI/MBL
BIU Implementation Principles
Since the KSZ8842M is an I/O device with 16 addressable locations, address decoding is based on the values of A15-A4
and AEN. Whenever DATACSN is asserted, the address decoder is disabled and a 32-bit transfer to Data Register is
assumed (BE3N – BE0N are ignored).
If address latching is required, the address is latched on the rising edge of ADSN and is transparent when ADSN=0.
1. Byte, word, and double-word data buses and accesses (transfers) are supported.
2. Internal byte swapping is not implemented and word swapping is supported internally. Refer to Figure 13 for the
appropriate 8-bit, 16-bit, and 32-bit data bus connection.
3. Since independent sets of synchronous and asynchronous signals are provided, synchronous and asynchronous
cycles can be mixed or interleaved as long as they are not active simultaneously.
4. The asynchronous interface uses RDN and WRN signal strobes for data latching. If necessary, ARDY is de-
asserted on the leading edge of the strobe.
5. The VLBUS-like synchronous interface uses BCLK, ADSN, and SWR and CYCLEN to control read and write
operations and generate SRDYN to insert the wait state, if necessary, when VLBUSN = 0. For read, the data must
be held until RDYRTNN is asserted.
6. The EISA-like burst transfer is supported using synchronous interface signals and DATACSN when I/O signal
VLBUSN = 1. Both the system/host/memory and KSZ8842M are capable of inserting wait states. To set the
system/host/memory to insert a wait state, assert RDYRTNN signal. To set the KSZ8842M to insert a wait state,
assert SRDYN signal.
Queue Management Unit (QMU)
The Queue Management Unit (QMU) manages packet traffic between the MAC/PHY interface and the system host. It has
built-in packet memory for receive and transmit functions called TXQ (Transmit Queue) and RXQ (Receive Queue). Each
queue contains 4KB of memory for back-to-back, non-blocking frame transfer performance. It provides a group of control
registers for system control, frame status registers for current packet transmit/receive status, and interrupts to inform the
host of the real time TX/RX status.
Transmit Queue (TXQ) Frame Format
The frame format for the transmit queue is shown in the following Table 3. The first word contains the control information
for the frame to transmit. The second word is used to specify the total number of bytes of the frame. The packet data
follows. The packet data area holds the frame itself. It may or may not include the CRC checksum depending on whether
hardware CRC checksum generation is enabled.
Multiple frames can be pipelined in both the transmit queue and receive queue as long as there is enough queue memory,
thus avoiding overrun. For each transmitted frame, the transmit status information for the frame is located in the TXSR
register.
Packet Memory Bit 15
Address Offset ₂nd _Byte
Bit 0
1^st Byte
0
Control Word
2
4 - up
Byte Count
Packet Data
(maximum size is 1916)
Table 3: Transmit Queue Frame Format
Since multiple packets can be pipelined into the TX packet memory for transmit, the transmit status reflects the status of
the packet that is currently being transferred on the MAC interface (which may or may not be the last queued packet in the
TX queue).
The transmit control word is the first 16-bit word in the TX packet memory, followed by a 16-bit byte count. It must be
word aligned. Each control word corresponds to one TX packet. Table 4 gives the transmit control word bit fields.
October 2007
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