KSZ8851-16MQL Datasheet, PDF (71/89 Pages) Micrel Semiconductor – Single-Port Ethernet MAC Controller with 8/16-Bit or 32-Bit Non-PCI Interface

Micrel, Inc.
KSZ8851-16/32 MQL/MQLI
15-1
-
0
0
RW
WO
(Self clear)
Reserved.
PHY Reset Bit
This bit is write only and self clear after write an “1”, it is used to reset PHY block circuitry.
0xDA – 0xDF: Reserved
0xE0 – 0xE3: Reserved
PHY 1 MII-Register Basic Control Register (0xE4 – 0xE5): P1MBCR
This register contains Media Independent Interface (MII) register for port 1 as defined in the IEEE 802.3 specification.
Bit
Default
R/W
15
0
RO
14
0
RW
13
1
RW
12
1
RW
11-10 0
RW
9
0
RW
8
1
RW
7-6
0
RO
5
1
R/W
4
0
RW
3
0
RW
2
0
RW
1
0
RW
0
0
RW
Description
Reserved
Local (far-end) loopback (llb)
1 = perform local loopback at host
(host Tx -> PHY -> host Rx, see Figure 11)
0 = normal operation
Force 100
1 = force 100Mbps if AN is disabled (bit 12)
0 = force 10Mbps if AN is disabled (bit 12)
AN Enable
1 = auto-negotiation enabled.
0 = auto-negotiation disabled.
Reserved
Restart AN
1 = restart auto-negotiation.
0 = normal operation.
Force Full Duplex
1 = force full duplex
0 = force half duplex.
if AN is disabled (bit 12) or AN is enabled but failed.
Reserved
HP_mdix
1 = HP Auto MDI-X mode.
0 = Micrel Auto MDI-X mode.
Force MDI-X
1 = force MDI-X.
0 = normal operation.
Disable MDI-X
1 = disable auto MDI-X.
0 = normal operation.
Reserved.
Disable Transmit
1 = disable transmit.
0 = normal operation.
Disable LED
1 = disable all LEDs.
0 = normal operation.
Bit is same as:
Bit 6 in P1CR
Bit 7 in P1CR
Bit 13 in P1CR
Bit 5 in P1CR
Bit 15 in P1SR
Bit 9 in P1CR
Bit 10 in P1CR
Bit 14 in P1CR
Bit 15 in P1CR
August 2009
71
M9999-083109-2.0