KSZ8851-16MQL Datasheet, PDF (38/89 Pages) Micrel Semiconductor – Single-Port Ethernet MAC Controller with 8/16-Bit or 32-Bit Non-PCI Interface

Micrel, Inc.
KSZ8851-16/32 MQL/MQLI
Receive Queue (RXQ) Frame Format
The frame format for the receive queue is shown in Table 9. The first word contains the status information for the frame
received. The second word is the total number of bytes of the RX frame. Following that is the packet data area. The
packet data area holds the frame itself. It includes the CRC checksum.
Packet Memory
Address Offset
0
2
4 - up
Bit 15
2^nd Byte
Bit 0
1^st Byte
Status Word (High byte and low byte need to swap in Big-
Endian mode. Also see description in RXFHSR register)
Byte Count (High byte and low byte need to swap in Big-
Endian mode. Also see description in RXFHBCR register)
Receive Packet Data
(maximum size is 2000)
Table 9. Frame Format for Receive Queue
Frame Receiving Path Operation in RXQ
This section describes the typical register settings for receiving packets from KSZ8851M to host processor with generic
bus interface. User can use the default value for most of the receive registers. The following Table 10 describes all
registers which need to be set and used for receiving single or multiple frames.
Register Name[bit](offset)
RXCR1(0x74)
RXCR2(0x76)
RXFHSR[15:0](0x7C)
RXFHBCR[11:0](0x7E)
RXQCR[12:3](0x82)
RXFDPR[14](0x86)
RXDTTR[15:0](0x8C)
RXDBCTR[15:0](0x8E)
IER[13](0x90)
ISR[15:0](0x92)
RXFCTR[15:8](0x9C)
RXFCTR[7:0](0x9C)
Description
Set receive control function as below:
Set RXCR1[10] to enable receiving flow control. Set RXCR1[0] to enable receiving block operation.
Set receive checksum check for ICMP, UDP, TCP and IP packet.
Set receive address filtering scheme as shown in the Table 3.
This register (read only) indicates the current received frame header status information.
This register (read only) indicates the current received frame header byte count information.
Set RXQ control function as below:
Set bit 3 to start DMA access from host CPU either read (receive frame data) or write (transmit data
frame). Set bit 4 to automatically enable RXQ frame buffer dequeue. Set bit 5 to enable RX frame count
threshold and read bit 10 for status. Set bit 6 to enable RX data byte count threshold and read bit 11 for
status. Set bit 7 to enable RX frame duration timer threshold and read bit 12 for status. Set bit 9 enable
RX IP header two-byte offset.
Set bit 14 to enable RXQ address register increments automatically on accesses to the data register.
To program received frame duration timer value. When Rx frame duration in RXQ exceeds this
threshold in 1µS interval count and bit 7 of RXQCR register is set to 1, the KSZ8851M will generate RX
interrupt in ISR[13] and indicate the status in RXQCR[12].
To program received data byte count value. When the number of received bytes in RXQ exceeds this
threshold in byte count and bit 6 of RXQCR register is set to 1, the KSZ8851M will generate RX
interrupt in ISR[13] and indicate the status in RXQCR[11].
Set bit 13 to enable receive interrupt in Interrupt Enable Register.
Write 1 (0xFFFF) to clear all interrupt status bits after interrupt occurred in Interrupt Status Register.
Rx frame count read only. To indicate the total received frame in RXQ frame buffer when receive
interrupt (bit 13 in ISR) occurred.
To program received frame count value. When the number of received frames in RXQ exceeds this
threshold value and bit 5 of RXQCR register is set to 1, the KSZ8851M will generate RX interrupt in
ISR[13] and indicate the status in RXQCR[10].
Table 10. Registers Setting for Receive Function Block
August 2009
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M9999-083109-2.0