KSZ8873MLL_13 Datasheet, PDF (64/115 Pages) Micrel Semiconductor – Integrated 3-Port 10/100 Managed Switch with PHYs

Micrel, Inc.
Register 19⁽⁵⁾ (0x13): Port 1 Control 3
Register 35 (0x23): Port 2 Control 3
Register 51 (0x33): Port 3 Control 3
Bit
Name
R/W Description
Port’s default tag, containing
Default Tag
7-0
R/W
[15:8]
7-5 : User priority bits
4 : CFI bit
3-0 : VID[11:8]
Register 20⁽⁵⁾ (0x14): Port 1 Control 4
Register 36 (0x24): Port 2 Control 4
Register 52 (0x34): Port 3 Control 4
Bit
Name
R/W Description
Default Tag
Port’s default tag, containing
7-0
R/W
[7:0]
7-0 : VID[7:0]
Note:
5. Registers 19 and 20 (and those corresponding to other ports) serve two purposes:
a. Associated with the ingress untagged packets, and used for egress tagging.
b. Default VID for the ingress untagged or null-VID-tagged packets, and used for address lookup.
KSZ8873MLL/FLL/RLL
Default
0x00
Default
0x01
Register 21 (0x15): Port 1 Control 5
Register 37 (0x25): Port 2 Control 5
Register 53 (0x35): Port 3 Control 5
Bit
Name
R/W Description
=1, Port 3 MII MAC mode
=0, Port 3 MII PHY mode
Default
Port 3 MII Mode
Note:
Inversion of
7
Selection
R/W ^{Bit 7 is reserved in the port 1 and port 2 of the port register control} power strapped value
5. But request to set the register 21 port 1 control 5 bit [7] = ‘1’ for
of SMRXDV3.
better EMI, because this bit 7 of the register 21 is for port 1 MII of
the MML part. In the MLL/FLL/RLL parts, setting this bit will disable
the unused internal 25MHz clock for the unused port 1 MII PHY
mode circuits.
Self-Address
Filtering Enable
=1, Enable port 1 self-address filtering MACA1
6
MACA1
R/W =0, Disable
0
(not for 0x35)
September 20, 2013
64
Revision 1.6