KSZ8873MLL_13 Datasheet, PDF (17/115 Pages) Micrel Semiconductor – Integrated 3-Port 10/100 Managed Switch with PHYs

Micrel, Inc.
KSZ8873MLL/FLL/RLL
Pin Description and I/O Assignment (Continued)
Pin Number
Pin Name
Type ⁽¹⁾
Description
Port 2 LED Indicators:
Default: Speed (refer to Register 195 bit[5:4])
Strap option: Serial bus configuration
Port 2 LED Indicators:
Default: Link/Act. (refer to Register 195 bit[5:4])
Strap option: Serial bus configuration
Serial bus configuration pins to select mode of access to KSZ8873MLL/FLL/RLL
internal registers.
[P2LED1, P2LED0] = [0, 0] — I²C master (EEPROM) mode
(If EEPROM is not detected, the KSZ8873MLL/FLL/RLL will be configured with the
default values of its registers and the values of its strap-in pins.)
Interface Signals Type Description
SPIQ
SCL_MDC
SDA_MDIO
O
Not used (tri-stated)
O
I²C clock
I/O
I²C data I/O
SPISN
I
Not used
[P2LED1, P2LED0] = [0, 1] — I²C slave mode
The external I²C master will drive the SCL_MDC clock.
60
P2LED1
Ipu/O _{The KSZ8873MLL/FLL/RLL device addresses are:}
1011_1111 <read>; 1011_1110 <write>
Interface Signals Type Description
SPIQ
SCL_MDC
SDA_MDIO
O
Not used (tri-stated)
I
I²C clock
I/O
I²C data I/O
SPISN
I
Not used
[P2LED1, P2LED0] = [1, 0] — SPI slave mode
Interface Signals Type Description
SPIQ
O
SPI data out
SCL_MDC
SDA_MDIO
I
SPI clock
I
SPI data In
SPISN
I
SPI chip select
[P2LED1, P2LED0] = [1, 1] – SMI/MIIM-mode
In SMI mode, the KSZ8873MLL/FLL/RLL provides access to all its internal 8-bit
registers through its SCL_MDC and SDA_MDIO pins.
In MIIM mode, the KSZ8873MLL/FLL/RLL provides access to its 16-bit MIIM
registers through its SDC_MDC and SDA_MDIO pins.
61
P2LED0
Ipu/O
62
RSTN
Ipu Hardware reset pin (active low)
September 20, 2013
17
Revision 1.6