KSZ8873MLL_13 Datasheet, PDF (61/115 Pages) Micrel Semiconductor – Integrated 3-Port 10/100 Managed Switch with PHYs

Micrel, Inc.
KSZ8873MLL/FLL/RLL
Register 16 (0x10): Port 1 Control 0
Register 32 (0x20): Port 2 Control 0
Register 48 (0x30): Port 3 Control 0 (Continued)
Bit
Name
R/W Description
=00, Ingress packets on port will be
classified as priority 0 queue if “Diffserv” or “802.1p” classification is not
enabled or fails to classify.
=01, Ingress packets on port will be
classified as priority 1 queue if “Diffserv” or “802.1p” classification is not
enabled or fails to classify.
4-3
Port-Based
Priority
R/W ^{=10, Ingress packets on port will be}
Classification
classified as priority 2 queue if “Diffserv” or “802.1p” classification is not
enabled or fails to classify.
=11, Ingress packets on port will be
classified as priority 3 queue if “Diffserv” or “802.1p” classification is not
enabled or fails to classify.
Note: “DiffServ”, “802.1p” and port priority can be enabled at the same time.
The OR’ed result of 802.1p and DSCP overwrites the port priority.
=1, When packets are output on the port, the switch will add 802.1p/q tags to
packets without 802.1p/q tags when received. The switch will not add tags to
packets already tagged. The tag inserted is the ingress port’s “port VID”.
2
Tag Insertion
R/W _{=0, Disable tag insertion}
Note: For the tag insertion available, the register 194 bits [5-0] have to be set
first.
=1, When packets are output on the port, the switch will remove 802.1p/q tags
from packets with 802.1p/q tags when received. The switch will not modify
1
Tag Removal
R/W _{packets received without tags.}
=0, Disable tag removal
=1, Split TXQ to 4 queue configuration. It cannot be enable at the same time
0 TXQ Split Enable R/W ^{with split 2 queue at register 18, 34,50 bit 7.}
=0, No split, treated as 1 queue configuration
Default
00
0
0
0
September 20, 2013
61
Revision 1.6