KSZ8091MNX Datasheet, PDF (43/83 Pages) Micrel Semiconductor – 10Base-T/100Base-TX Physical Layer Transceiver

Micrel, Inc.
KSZ8091MNX/KSZ8091RNB
Customized-Packet Detection
The customized packet has associated register/bit masks to select which byte, or bytes, of the first 64 bytes of the packet
to use in the CRC calculation. After the KSZ8091MNX/RNB receives the packet from its link partner, the selected bytes
for the received packet are used to calculate the CRC. The calculated CRC is compared to the expected CRC value that
was previously written to and stored in the KSZ8091MNX/RNB PHY Registers. If there is a match, the
KSZ8091MNX/RNB asserts its PME output pin low.
Four customized packets are provided to support four types of wake-up scenarios. A dedicated set of registers is used to
configure and enable each customized packet.
The following MMD Registers are provided for customized-packet detection:
• Each of the four customized packets is enabled via MMD address 1Fh, Register 0h,
− Bit [2] // For customized packets, type 0
− Bit [3] // For customized packets, type 1
− Bit [4] // For customized packets, type 2
− Bit [5] // For customized packets, type 3
• Masks to indicate which of the first 64-bytes to use in the CRC calculation are set in:
− MMD address 1Fh, Registers 1h – 4h // For customized packets, type 0
− MMD address 1Fh, Registers 7h – Ah // For customized packets, type 1
− MMD address 1Fh, Registers Dh – 10h // For customized packets, type 2
− MMD address 1Fh, Registers 13h – 16h // For customized packets, type 3
• 32-bit expected CRCs are written to and stored in:
− MMD address 1Fh, Registers 5h – 6h // For customized packets, type 0
− MMD address 1Fh, Registers Bh – Ch // For customized packets, type 1
− MMD address 1Fh, Registers 11h – 12h // For customized packets, type 2
− MMD address 1Fh, Registers 17h – 18h // For customized packets, type 3
Link Status Change Detection
If link status change detection is enabled, the KSZ8091MNX/RNB asserts its PME output pin low whenever there is a link
status change, using the following MMD address 1Fh register bits and their enabled (1) or disabled (0) settings:
• MMD address 1Fh, Register 0h, bit [0]
// For link-up detection
• MMD address 1Fh, Register 0h, bit [1]
// For link-down detection
The PME output signal is available on either INTRP/PME_N2 (pin 21) or LED0/PME_N1 (pin 30), and is enabled using
standard Register 16h, bit [15]. MMD address 1Fh, Register 0h, bits [15:14] defines and selects the output functions for
pins 21 and 30.
The PME output is active low and requires a 1kΩ pull-up to the VDDIO supply. When asserted, the PME output is cleared
by disabling the register bit that enabled the PME trigger source (magic packet, customized packet, link status change).
August 31, 2015
43
Revision 1.2