KSZ8091MNX Datasheet, PDF (17/83 Pages) Micrel Semiconductor – 10Base-T/100Base-TX Physical Layer Transceiver

Micrel, Inc.
KSZ8091MNX/KSZ8091RNB
Strapping Options – KSZ8091RNB
Pin Number Pin Name
Type⁽⁶⁾ Pin Function
15
PHYAD2
Ipd/O PHYAD[2:0] is latched at de-assertion of reset and is configurable to any value from 0 to
14
PHYAD1
Ipd/O ^{7 with PHY Address 1 as the default value.}
13
PHYAD0
Ipu/O
PHY Address 0 is assigned by default as the broadcast PHY address, but it can be
assigned as a unique PHY address after pulling the B-CAST_OFF strapping pin high or
writing a ‘1’ to Register 16h, bit [9].
PHY Address bits [4:3] are set to 00 by default.
18
CONFIG2
Ipd/O The CONFIG[2:0] strap-in pins are latched at the de-assertion of reset.
29
CONFIG1
Ipd/O
CONFIG[2:0]
Mode
28
CONFIG0
Ipd/O
001
RMII
101
RMII back-to-back
000, 010–100, 110, 111 Reserved – not used
22
PME_EN
Ipd/O PME output for Wake-on-LAN
Pull-up = Enable
Pull-down (default) = Disable
At the de-assertion of reset, this pin value is latched into Register 16h, bit [15].
20
ISO
Ipd/O Isolate mode
Pull-up = Enable
Pull-down (default) = Disable
At the de-assertion of reset, this pin value is latched into register 0h, bit [10].
31
SPEED
Ipu/O Speed mode
Pull-up (default) = 100Mbps
Pull-down = 10Mbps
At the de-assertion of reset, this pin value is latched into Register 0h, bit [13] as the
speed select, and also is latched into Register 4h (auto-negotiation advertisement) as
the speed capability support.
16
DUPLEX
Ipu/O Duplex mode
Pull-up (default) = Half-duplex
Pull-down = Full-duplex
At the de-assertion of reset, this pin value is latched into Register 0h, bit [8].
30
NWAYEN
Ipu/O Nway auto-negotiation enable
Pull-up (default) = Enable auto-negotiation
Pull-down = Disable auto-negotiation
At the de-assertion of reset, this pin value is latched into Register 0h, bit [12].
19
B-CAST_OFF Ipd/O Broadcast off – for PHY Address 0
Pull-up = PHY Address 0 is set as an unique PHY address
Pull-down (default) = PHY Address 0 is set as a broadcast PHY address
At the de-assertion of reset, this pin value is latched by the chip.
21
NAND_Tree# Ipu/Opu NAND tree mode
Pull-up (default) = Disable
Pull-down = Enable
At the de-assertion of reset, this pin value is latched by the chip.
The strap-in pins are latched at the de-assertion of reset. In some systems, the MAC RMII receive input pins may drive high/low during
power-up or reset, and consequently cause the PHY strap-in pins on the RMII signals to be latched to unintended high/low states. In
this case, external pull-ups (4.7kΩ) or pull-downs (1.0kΩ) should be added on these PHY strap-in pins to ensure that the intended
values are strapped-in correctly.
August 31, 2015
17
Revision 1.2