PL602081UMG Datasheet, PDF (4/15 Pages) Micrel Semiconductor – PCIe Octal, Ultra-Low Jitter, HCSL Frequency Synthesizer

Micrel, Inc.
Pin Description (Continued)
Pin Number
Pin Name
Pin Type
9
PLL_BYPASS
I, (SE)
10
11, 20, 27,
30, 34
17
18
19
15
22
XTAL_SEL
TEST
REF_IN
XTAL_IN
XTAL_OUT
OE1
OE2
I, (SE)
I, (SE)
I, (SE)
O, (SE)
I, (SE)
I, (SE)
PL60208X
Pin Level
LVCMOS
LVCMOS
LVCMOS
10pF crystal
10pF crystal
LVCMOS
LVCMOS
Pin Name
PLL bypass, selects output source.
0 = normal PLL operation
1 = output from input reference clock or crystal
45KΩ pull down
Selects PLL input reference source
0 = REF_IN, 1 = XTAL, 45KΩ pull-up
Factory test pins. Do not connect anything to these pins.
Reference clock input
Crystal reference input, no load caps needed (see Figure 6)
Crystal reference output, no load caps needed (see Figure
6)
Output enable, outputs Q0 – Q3 disable to tri-state,
0 = disabled, 1 = enabled, 45KΩ pull-up
Output enable, outputs Q4 – Q7 disable to tri-state,
0 = disabled, 1 = enabled, 45KΩ pull-up
December 11, 2013
4
Revision 1.1
[e-mail] or [phone]