PIC24FV32KA304-I Datasheet, PDF (37/320 Pages) Microchip Technology – 20/28/44/48-Pin, General Purpose, 16-Bit Flash Microcontrollers with XLP Technology

PIC24FV32KA304 FAMILY
4.0 MEMORY ORGANIZATION
As Harvard architecture devices, the PIC24F
microcontrollers feature separate program and data
memory space and bussing. This architecture also
allows the direct access of program memory from the
data space during code execution.
4.1 Program Address Space
The program address memory space of the
PIC24FV32KA304 family is 4M instructions. The space
is addressable by a 24-bit value derived from either the
23-bit Program Counter (PC) during program execution,
or from a table operation or data space remapping, as
described in Section 4.3 “Interfacing Program and
Data Memory Spaces”.
User access to the program memory space is restricted
to the lower half of the address range (000000h to
7FFFFFh). The exception is the use of TBLRD/TBLWT
operations, which use TBLPAG<7> to permit access to
the Configuration bits and Device ID sections of the
configuration memory space.
Memory maps for the PIC24FV32KA304 family of
devices are shown in Figure 4-1.
FIGURE 4-1:
PROGRAM SPACE MEMORY MAP FOR PIC24FV32KA304 FAMILY DEVICES
PIC24FV16KA304
GOTO Instruction
Reset Address
Interrupt Vector Table
Reserved
Alternate Vector Table
Flash
Program Memory
(5632 instructions)
PIC24FV32KA304
GOTO Instruction
Reset Address
Interrupt Vector Table
Reserved
Alternate Vector Table
000000h
000002h
000004h
0000FEh
000100h
000104h
0001FEh
000200h
User Flash
Program Memory
(11264 instructions)
002BFEh
Unimplemented
Read ‘0’
Data EEPROM
Reserved
Device Config Registers
Reserved
DEVID (2)
Note: Memory areas are not displayed to scale.
Unimplemented
Read ‘0’
Data EEPROM
Reserved
0057FEh
7FFE00h
7FFFFFh
800000h
Device Config Registers
F7FFFEh
F80000h
F80010h
F80012h
Reserved
DEVID (2)
FEFFFEh
FF0000h
FFFFFFh
DS39995B-page 37
 2011 Microchip Technology Inc.