PIC24FV32KA304-I Datasheet, PDF (216/320 Pages) Microchip Technology – 20/28/44/48-Pin, General Purpose, 16-Bit Flash Microcontrollers with XLP Technology

PIC24FV32KA304 FAMILY
REGISTER 22-2: AD1CON2: A/D CONTROL REGISTER 2
R/W-0
PVCFG1
bit 15
R/W-0
PVCFG0
R/W-0
NVCFG0
R/W-0
OFFCAL
R/W-0
BUFREGEN
R/W-0
CSCNA
R/W-0
BUFS⁽¹⁾
bit 7
R/W-0
SMPI4
R/W-0
SMPI3
R/W-0
SMPI2
R/W-0
SMPI1
R/W-0
SMPI0
U-0
—
R/W-0
BUFM⁽¹⁾
U-0
—
bit 8
R/W-0
ALTS
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
bit 13
bit 12
bit 11
bit 10
bit 9-8
bit 7
bit 6-2
bit 1
bit 0
PVCFG<1:0>: Converter Positive Voltage Reference Configuration bits
11 = Internal VRH2
10 = Internal VRH1
01 = External VREF+
00 = AVDD
NVCFG0: Converter Negative Voltage Reference Configuration bits
1 = External VREF-
0 = AVSS
OFFCAL: Offset Calibration Mode Select bit
1 = Inverting and non-inverting inputs of channel Sample-and-Hold are connected to AVSS
0 = Inverting and non-inverting inputs of channel Sample-and-Hold are connected to normal inputs
BUFREGEN: A/D Buffer Register Enable bit
1 = Conversion result is loaded into buffer location determined by the converted channel
0 = A/D result buffer is treated as a FIFO
CSCNA: Scan Input Selections for CH0+ During SAMPLE A bit
1 = Scan inputs
0 = Do not scan inputs
Unimplemented: Read as ‘0’
BUFS: Buffer Fill Status bit⁽¹⁾
1 = A/D is filling the upper half of the buffer; user should access data in the lower half
0 = A/D is filling the lower half of the buffer; user should access data in the upper half
SMPI<4:0>: Interrupt Sample Rate Select bits
11111 = Interrupts at the completion of conversion for each 32nd sample
11110 = Interrupts at the completion of conversion for each 31st sample



00001 = Interrupts at the completion of conversion for every other sample
00000 = Interrupts at the completion of conversion for each sample
BUFM: Buffer Fill Mode Select bit⁽¹⁾
1 = Starts buffer filling at AD1BUF0 on first interrupt and AD1BUF(n/2) on next interrupt
(Split Buffer mode)
0 = Starts filling buffer at address, ADCBUF0, and each sequential address on successive interrupts
(FIFO mode)
ALTS: Alternate Input Sample Mode Select bit
1 = Uses channel input selects for SAMPLE A on first sample and SAMPLE B on next sample
0 = Always uses channel input selects for SAMPLE A
Note 1: Only applicable when the buffer is used in FIFO mode (BUFREGEN = 0). In addition, BUFS is only used
when BUFM = 1.
DS39995B-page 216
 2011 Microchip Technology Inc.