PL902XXX Datasheet, PDF (3/10 Pages) Micrel Semiconductor – Lowest power and smallest programmable jitter attenuator

Micrel, Inc.
PL902xxx
Functional Description
The PL902xxx series is a highly featured, very flexible, advanced programmable jitter filter design for high performance,
low-power, small form-factor applications. The PL902xxx accepts a reference clock input between 1MHz and 200MHz and
is capable of producing up to three outputs in the 5MHz to 200MHz range. The most common configuration will be
comprised of the same input and output frequency, but this flexible design also allows frequency translation from one
frequency to another frequency as long as both frequencies are within the specified ranges for input and output.
Jitter Filter Programming
Typically, the jitter filter settings will be optimized for one
particular input and output frequency, but the flexible
design also allows configurations for a certain frequency
range, up to one octave wide.
The typical bandwidth of the jitter filter is 4kHz. This means
that jitter frequency components above 4kHz will be
attenuated. In case of frequency translation, the bandwidth
may be slightly different.
Clock Output (CLK0)
CLK0 is the main clock output. The output drive level can
be programmed to low drive (4mA), standard drive (8mA)
or high drive (16mA). The maximum output frequency is
200MHz at 3.3V operation and 167MHz at 2.5V operation.
Clock Output (CLK1, CLK2)
The CLK1 and CLK2 feature allows the PL902xxx to have
two additional clock outputs programmed to one of the
following frequencies:
 CLK1 = CLK0
 CLK2 = CLK0, CLK0/2 or CLK0/4
CLK1 and CLK2 allow the same output drive level
programming as CLK0. Because of the extra /2 and /4
settings, CLK2 is capable of going down to 1.25MHz. In
case only an output clock of <5MHz is needed, CLK0 and
CLK1 can be disabled.
Output Enable (OE)
The output enable feature allows the user to enable and
disable the clock output(s) by toggling the OE pin. The OE
pin incorporates a 60kΩ pull-up resistor, giving a default
condition of logic “1”.
Power Down Control (PDB)
The power down (PDB) feature allows the user to put the
PL902xxx into sleep mode. When activated (logic “0”),
PDB disables the synthesizer circuitry, counters, and all
other active circuitry. In power down mode, the IC
consumes <10µA of power. The PDB pin incorporates a
60kΩ pull-up resistor giving a default condition of logic “1”.
Configuration Select (CSEL)
The configuration select (CSEL) feature allows the
PL902xxx to switch between two pre-programmed
configurations allowing the device on-the-fly frequency
switching. The CSEL pin incorporates a 60kΩ pull-up
resistor giving a default condition of logic “1”.
Examples for this feature are:
 Select between two frequencies or two frequency
ranges.
 Select between two frequency translations, like 1:1
and 1:2.
August 1, 2014
3
Revision 1.1
[e-mail] or [phone]