MIC24046-H Datasheet, PDF (3/24 Pages) Micrel Semiconductor – Pin-Programmable, 4.5V − 19V, 5A Step-Down Converter

Micrel, Inc.
MIC24046-H
Pin Description (Continued)
Pin Number
11
12
14
15
16
17
18
19
20
PGND_EP
VIN_EP
LX_EP
Pin Name
ILIM
FREQ
AGND
COMP
OUTSNS
EN/DLY
VDDA
VDDP
VINLDO
PGND
VIN
LX
Pin Function
Three-State (Low, High, and High-Z) Current-Limit Selection Pin.
Three-State (Low, High, and High-Z) Switching Frequency Selection Pin.
Analog Ground: Quiet ground for the analog circuitry of the internal regulator and return terminal for
the external compensation network.
Transconductance Error Amplifier Output: Connect a compensation network from this pin to AGND.
Output Sensing: Connect this pin directly to the buck converter output voltage. This pin is the top side
terminal of the internal feedback divider.
Precision Enable/Turn-On Delay Input. The EN/DLY pin is first compared against a 507mV threshold
to turn-on the on-board LDO regulator. The EN/DLY pin is then compared against a 1.21V (typical)
threshold to initiate output power delivery. A 150mV typical hysteresis prevents chattering when
power delivery is started. A 2µA (typical) current source pulls up the EN/DLY pin. Turn-on delay can
be achieved by connecting a capacitor from EN/DLY to ground, while using an open-drain output to
drive the EN/DLY pin.
Output of the internal linear regulator and internal supply for analog control. A 1µF minimum ceramic
capacitor should be connected from this pin to AGND; 2.2µF nominal value recommended.
Internal Supply Rail for the MOSFET Drivers (fed by the VDDA pin): An internal resistor (10Ω)
between pins VDDP and VDDA is provided in the regulator in order to implement an RC filter for
switching noise suppression. A 1µF minimum ceramic capacitor should be connected from this pin to
PGND; 2.2µF nominal value recommended.
Input of the Internal Linear Regulator: This pin is typically connected to the input voltage of the buck
converter stage (VIN). If VINLDO and VIN are connected to different voltage rails, individually bypass
VINLDO to ground with a 100nF ceramic capacitor.
PGND Exposed Pad: Electrically connected to PGND pins. Connect with thermal vias to the ground
plane to ensure adequate heat-sinking. Follow recommendations as illustrated in the PCB Layout
Recommendations section
VIN Exposed Pad: Electrically connected to VIN pins. If an input power distribution plane is available,
connect with thermal vias to that plane to improve heat-sinking. Follow recommendations as
illustrated in the PCB Layout Recommendations section
LX Exposed Pad: Electrically connected to LX pins. Follow recommendations as illustrated in the
PCB Layout Recommendations section
July 7, 2015
3
Revision 1.1