MIC24046-H Datasheet, PDF (18/24 Pages) Micrel Semiconductor – Pin-Programmable, 4.5V − 19V, 5A Step-Down Converter

Micrel, Inc.
The procedure for compensation design follows these
steps:
1. Set the T_V(S) loop gain crossover frequency f_XO in the
range f_S/20 to f_S/10. Lower values of f_XO permit a
more predictable and robust phase margin. Higher
values of f_XO would involve additional considerations
about the current loop bandwidth in order to achieve
a robust phase margin, therefore a more
conservative approach is highly recommended:
f_XO
≈
f_S
20
Eq. 19
2. Select R_C1 to achieve the target crossover frequency
f_XO of the overall voltage loop. This typically happens
where the power stage transfer function G_CO(S) is
rolling off at -20dB/dec. The compensator transfer
function H_C(S) is in the so-called mid-band gain region
where C_C1 can be considered a DC-blocking short
circuit while C_C2 can still be considered as an open
circuit, as illustrated in Equation 20:
R _C1
=


R1+ R2
R1


⋅
2π × C_O × f_XO
Gm_EA ⋅ Gm_PS
Eq. 20
3. Select capacitor C_C1 to place the compensator zero
at the load pole. The load pole moves around with
load variations, so to calculate the load pole use as a
load resistance R_L the value determined by the
nominal output current I_O of the application, as shown
in Equation 21 and Equation 22:
R_L
=
V_O
I_O
Eq. 21
C_C1
=
C_O
× (ESR
R_C1
+
R_L
)
Eq. 22
4. Select capacitor C_C2 to place the compensator pole at
the frequency of the output capacitor ESR zero, or at
≥ 5 f_XO, whichever is lower.
MIC24046-H
C_C2 is intended to place the compensator pole at the
frequency of the output capacitor ESR zero, and/or to
achieve additional switching ripple/noise attenuation.
If the output capacitor is a polarized one, its ESR zero will
typically occur at low enough frequencies to cause the
loop gain to flatten out and not roll-off at a -20 dB/decade
slope around or just after the crossover frequency f_XO.
This is undesirable, because of scarce compensation
design robustness, and because of switching noise
susceptibility. The compensator pole is then used to
cancel the output capacitor ESR zero and to achieve a
well-behaved roll-off of the loop gain above the crossover
frequency.
If the output capacitors are only ceramic ones, their ESR
zeroes frequencies could be very high (in many cases
even above the switching frequency itself). Loop gain roll-
off at −20dB/decade well beyond the crossover frequency
is ensured, but even in this case, it is good practice to still
make use of the compensator pole to further attenuate
switching noise, while conserving phase margin at the
crossover frequency. For example, setting the
compensator pole at 5 f_XO, will limit its associated phase
loss at the crossover frequency to about 11°. Placement
at even higher frequencies N × f_XO (N > 5) will reduce
phase loss even further, at the expense of less
noise/ripple attenuation at the switching frequency. Some
attenuation of the switching frequency noise/ripple is
achieved as long as N × f_XO < f_S.
For polarized output capacitor, compensator pole
placement at the ESR zero frequency is achieved shown
in Equation 23:
C_C2 =
1
R_{C1 −} 1
C_O × ESR C_C1
Eq. 23
For ceramic output capacitor, compensator pole
placement at N × f_XO (N ≥ 5, N × f_XO < f_S) is achieved as
detailed in Equation 24:
C_C2
=
1
2π × R_C1 × N × f_XO
−
1
C_C1
Eq. 24
July 7, 2015
18
Revision 1.1