MIC2591B_05 Datasheet, PDF (27/34 Pages) Micrel Semiconductor – Dual-Slot PCI Express Hot-Plug Controller

MIC2591B
Status Register Slot A (STATA)
8-Bits, Read-Only
Status Register, Slot A (STATA)
D[7]
D[6]
D[5]
D[4]
D[3]
read-only
read-only
read-only
read/write
read-only
FAULTA
MAINA
VAUXA
VAUXAF
Reserved
D[2]
read/write
12VAF
Micrel
D[1]
read-only
Reserved
D[0]
read/write
3VAF
Bit(s)
Function
FAULTA FAULT Status - Slot A
MAINA
MAIN Enable Status - Slot A
two Main Power outputs for Slot A
VAUXA
VAUX Enable Status - Slot A
Auxiliary Power output for Slot A
VAUXAF
D[3]
12VAF
D[1]
3VAF
Overcurrent Fault: VAUXA supply
Reserved
Overcurrent Fault: +12V supply
Reserved
Overcurrent Fault: 3.3V supply
Operation
1 = Fault pin asserted
(/FAULTA pin is LOW)
0 = Fault pin deasserted
(/FAULTA pin is HIGH)
See Notes 1, 2, and 3.
Represents the actual state (on/off) of the
(+12V and +3.3V)
1 = Main Power ON
0 = Main Power OFF
Represents the actual state (on/off) of the
1 = AUX Power ON
0 = AUX Power OFF
1 = Fault 0 = No fault
Always read as zero
1 = Fault 0 = No fault
Always read as zero
1 = Fault 0 = No fault
Power-Up Default Value:
Command_Byte Value (R/W):
0000 0000_b = 00_h
0000 0100_b = 04_h
The power-up default value is 00_h. Both slots are disabled upon power-up, i.e., all supply outputs are off. In response to an
overcurrent fault condition, writing a logical 1 back into the active (or set) bit position will clear the bit and deassert /INT. The
status of the /FAULTA pin is not affected by reading the Status Register or by clearing active status bits.
Notes:
1. If FAULTA has been set by an overcurrent condition on one or more of the MAIN outputs, the ONA input must go LOW to reset FAULTA.
If FAULTA has been set by a VAUXA overcurrent event, the AUXENA input must go LOW to reset FAULTA.
If an overcurrent has occurred on both a MAIN output and the VAUX output of slot A, both ONA and AUXENA of the slot must go low to reset
FAULTA.
2. Neither the FAULTA bits nor the /FAULTA pins are active when the MIC2591B power paths are controlled by the System Management Interface.
When using SMI power path control, AUXENA and ONA pins for that slot must be tied to GND.
3. If /FORCE_ONA is asserted (low), the /FAULTA pin will be unconditionally forced to its open-drain state. Note, though, that the value in the FAULTA
register bit is not affected by /FORCE_ONA, but will instead continue to read as a high if no faults are present on Slot A, and as a low if any fault
conditions exist which would disable Slot A if /FORCE_ONA was not asserted.
March 2005
27
M9999-033105