MIC2591B_05 Datasheet, PDF (21/34 Pages) Micrel Semiconductor – Dual-Slot PCI Express Hot-Plug Controller

MIC2591B
of the fault conditions listed above and deasserted when
one or all STAT[A/B] Register Bits D[4], D[2], D[0] and/or CS
Register Bits D[2], D[1] are reset upon the execution of an
SMBus “echo reset” WRITE_BYTE cycle. For polled-mode
operation, the INTMSK bit should be set to Logical “1,” thereby
inhibiting /INT output pin operation.
For those SMI-control applications where the /FORCE_ON[A/B]
inputs are needed for diagnostic purposes, the /FORCE_ON[A/B]
inputs must be enabled; that is, CNTRL[A/B] Register Bit
D[2] should read Logical “0.” Once /FORCE_ON[A/B] inputs
are asserted, all output voltages are present with all circuit
protection features disabled, including overtemperature pro-
tection on VAUX[A/B] outputs. To inhibit /FORCE_ON[A/B]
operation, a Logical “1” shall be written to the CNTRL[A/B]
Register Bit D[2] location(s).
HPI-only Control Applications
In applications where the MIC2591B is controlled only by the
HPI, SMBus signals SCL, SDA, and /INT signals are con-
nected to V_STBY as shown in Figure 6. In this configuration,
the MIC2591B’s /FAULT[A/B] outputs are activated after
power-on-reset and become asserted when:
Either or both external ON[A/B] and AUXEN[A/B] input signals
Micrel
are asserted, AND
• 12VIN[A/B], 3VIN[A/B], or VSTBY[A/B] input volt-
age is lower than its respective ULVO threshold,
OR
• The fast OC circuit breaker[A/B] has tripped, OR
• The slow OC circuit breaker[A/B] has tripped AND
its filter timeout[A/B] has expired, OR
• The slow OC circuit breaker[A/B] has tripped AND
Slot[A/B] die temperature > 140°C, OR
• The MIC2591B’s global die temperature > 160°C
In order to clear /FAULT[A/B] outputs once asserted, either
or both ON[A/B] and AUXEN[A/B] input signals must be
deasserted. Please see /FAULT[A/B] pin description for ad-
ditional information.
If the /FORCE_ON[A/B] inputs are used for diagnostic pur-
poses, both /FAULT[A/B] and /PWRGD[A/B] outputs are
deasserted once /FORCE_ON[A/B] inputs are asserted.
Serial Port Operation
The MIC2591B uses standard SMBus Write_Byte and
Read_Byte operations for communication with its host. The
SMBus Write_Byte operation involves sending the device’s
VSTBY
UVLO
+3.3V
0
AUXEN[A/B]
V_IH
0
tPOR
VAUX_OUT[A/B]
0
I_LIM(AUX)
I_{AUX_OUT[A/B]}
I_STEADY-STATE
0
ON[A/B]
0
12VOUT[A/B]
0
3VOUT[A/B]
0
/PWRGD_[A/B]
0
I_LIM(3V)
I_3VOUT[A/B]
I_STEADY-STATE
0
V_IL
V_IH
tFLT
V_IH
V_IH
V_IL
tFLT
/FAULT_[A/B] ₀
/INT*
0
*
*
* /INT de-asserted by software
Figure 9. Hot-Plug Interface Operation
March 2005
21
M9999-033105