MIC2591B_05 Datasheet, PDF (25/34 Pages) Micrel Semiconductor – Dual-Slot PCI Express Hot-Plug Controller

MIC2591B
Micrel
Control Register, Slot A (CNTRLA)
8-Bits, Read/Write
Control Register, Slot A (CNTRLA)
D[7]
D[6]
D[5]
D[4]
D[3]
read-only
read-only
read only
read only
read-only
AUXAPG
MAINAPG Reserved
Reserved
Reserved
D[2]
read/write
/FORCE_A
ENABLE
D[1]
read/write
MAINA
D[0]
read/write
VAUXA
Bit(s)
Function
AUXAPG AUX output power-good status, Slot A
MAINAPG MAIN output power-good status, Slot A
D[5]
D[4]
D[3]
/FORCE_A
ENABLE
MAINA
VAUXA
thresholds)
Reserved
Reserved
Reserved
Allows or inhibits the operation of the /FORCE_ONA
input pin
MAIN enable control, Slot A
VAUX enable control, Slot A
Operation
1 = Power-is-Good
(VAUXA Output is above its UVLO
threshold)
1 = Power-is-Good
(MAINA Outputs are above their UVLO
Always read as zero
Always read as zero
Always read as zero
0 = /FORCE_ONA is enabled
1 = /FORCE_ONA is disabled
0 = Off, 1 = On
0 = Off, 1 = On
Power-Up Default Value:
Read Command_Byte Value (R/W):
0000 0000_b = 00_h
0000 0010_b = 02_h
The power-up default value is 00_h. Slot is disabled upon power-up, i.e., all supply outputs are off.
Notes:
1. The state of the /PWRGDA pin is the logical AND of the values of the AUXAPG and the MAINAPG bits, except when /FORCE_ONA is asserted. If
/FORCE_ONA is asserted (the pin is pulled low), and /FORCE_AENABLE is set to a logic zero, the /PWRGDA pin will be unconditionally forced to
its open-drain (“Power Not Good”) state.
2. The values of the MAINAPG and AUXAPG register bits are not affected by /FORCE_ONA, but will instead continue to read as high if power is
“Good,” and as low if the conditions which indicate that power is good are not met.
March 2005
25
M9999-033105