MIC2555_06 Datasheet, PDF (27/29 Pages) Micrel Semiconductor – USB – OTG Transceiver

Micrel, Inc.
MIC2555
GPIO Interrupt Mask False
Set & Clear
GPIO_0
GPIO_1
GPIO_2
1
rd/s/c
1
rd/s/c
1
rd/s/c
1
rd/s/c
1
rd/s/c
1
rd/s/c
1
rd/s/c
1
rd/s/c
set – 1Ch
clr – 1Dh
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
Enables interrupts on transition from TRUE to FALSE
1 Æset = 1, Interrupt on TÆF.
1 Æclr = 0, no interrupt.
GPIO Interrupt Mask True
Set & Clear
set – 1Eh
clr – 1Fh
Enables interrupts on transition from FALSE to
TRUE.
1 Æset = 1, Interrupt on FÆT.
1 Æclr = 0, no interrupt.
GPIO_0
1
rd/s/c
bit 0
GPIO_1
1
rd/s/c
bit 1
GPIO_2
1
rd/s/c
bit 2
1
rd/s/c
bit 3
1
rd/s/c
bit 4
1
rd/s/c
bit 5
1
rd/s/c
bit 6
1
rd/s/c
bit 7
Note:
Access type “rd/s/c” denotes a field that can be read, set to 1 or cleared to 0. The register can be read from either of
the Addresses indicated. When writing to the “set” Address, any 1’s that are written cause the associated bit to be set.
When writing to the “clr” (Clear) Address, any 1s that are written cause the associated bit to be cleared.
Example Serial Controller Register Settings
Example
Location
Target register
‘Set’ register
Target register
‘Clear’ register
Target register
Condition
Initial state
Data loaded into ‘set’
register
Resulting state
Data loaded into
‘Clear’ register
Resulting state
BIT 7
0
1
1
1
0
BIT 6
0
0
0
0
0
BIT 5
1
0
1
0
1
BIT 4
0
0
0
0
0
BIT 3
1
1
1
1
0
BIT 2
0
0
0
0
0
BIT 1
0
0
0
0
0
BIT 0
0
0
0
0
0
December 2006
27
M9999-121406