KSZ8051MNL Datasheet, PDF (24/59 Pages) Micrel Semiconductor – 10Base-T/100Base-TX Physical Layer Transceiver

Micrel, Inc.
KSZ8051MNL/RNL
RMII Data Interface (KSZ8051RNL only)
The Reduced Media Independent Interface (RMII) specifies a low pin count Media Independent Interface (MII). It provides
a common interface between physical layer and MAC layer devices, and has the following key characteristics:
• Pin count is 8 pins (3 pins for data transmission, 4 pins for data reception, 1 pin for the 50MHz reference clock).
• 10Mbps and 100Mbps data rates are supported at both half and full duplex.
• Data transmission and reception are independent and belong to separate signal groups.
• Transmit data and receive data are each 2-bit wide, a dibit.
RMII – 25MHz Clock Mode
The KSZ8051RNL is configured to RMII – 25MHz Clock Mode after it is powered up or hardware reset with the following:
• A 25MHz crystal connected to XI, XO (pins 9, 8), or an external 25MHz clock source (oscillator) connected to XI.
• The CONFIG[2:0] strapping pins (pins 18, 29, 28) set to ‘001’.
• Register 1Fh, bit 7 is set to ‘0’ (default value) to select 25MHz Clock Mode.
RMII – 50MHz Clock Mode
The KSZ8051RNL is configured to RMII – 50MHz Clock Mode after it is powered up or hardware reset with the following:
• An external 50MHz clock source (oscillator) connected to XI (pin 9).
• The CONFIG[2:0] strapping pins (pins 18, 29, 28) set to ‘001’.
• Register 1Fh, bit 7 is set to ‘1’ to select 50MHz Clock Mode.
RMII Signal Definition
The following table describes the RMII signals. Refer to RMII Specification v1.2 for detailed information.
RMII
Signal Name
REF_CLK
TXEN
TXD[1:0]
CRS_DV
RXD[1:0]
RXER
Direction
(with respect to PHY,
KSZ8051RNL signal)
Output (25MHz clock mode) /
<no connect> (50MHz clock
mode)
Input
Input
Output
Output
Output
Direction
(with respect to
MAC)
Input /
Input or <no connect>
Description
Synchronous 50 MHz reference clock for
receive, transmit and control interface
Output
Output
Input
Input
Input, or (not
required)
Transmit Enable
Transmit Data [1:0]
Carrier Sense/Receive Data Valid
Receive Data [1:0]
Receive Error
Table 2. RMII Signal Description
Reference Clock (REF_CLK)
REF_CLK is a continuous 50MHz clock that provides the timing reference for TX_EN, TXD[1:0], CRS_DV, RXD[1:0], and
RX_ER.
For 25MHz Clock Mode, the KSZ8051RNL generates and outputs the 50MHz RMII REF_CLK to the MAC at REF_CLK
(pin 19).
For 50MHz Clock Mode, the KSZ8051RNL takes in the 50MHz RMII REF_CLK from the MAC or system board at XI (pin
9) and has the REF_CLK (pin 19) left as a no connect.
July 2010
24
M9999-070910-1.0