KSZ8051MNL Datasheet, PDF (10/59 Pages) Micrel Semiconductor – 10Base-T/100Base-TX Physical Layer Transceiver

Micrel, Inc.
KSZ8051MNL/RNL
Pin Description – KSZ8051MNL
Pin Number Pin Name
Type^{(1) Pin Function}
1
GND
Gnd
Ground
2
VDD_1.2
P
1.2V core V_DD (power supplied by KSZ8051MNL)
Decouple with 2.2uF and 0.1uF capacitors to ground.
3
VDDA_3.3
P
3.3V analog V_DD
4
RXM
I/O
Physical receive or transmit signal (- differential)
5
RXP
I/O
Physical receive or transmit signal (+ differential)
6
TXM
I/O
Physical transmit or receive signal (- differential)
7
TXP
I/O
Physical transmit or receive signal (+ differential)
8
XO
O
Crystal feedback – for 25 MHz crystal
This pin is a no connect if oscillator or external clock source is used.
9
XI
I
Crystal / Oscillator / External Clock Input
25MHz +/-50ppm
10
REXT
I
Set physical transmit output current
Connect a 6.49KΩ resistor to ground on this pin.
11
MDIO
I/O
Management Interface (MII) Data I/O
This pin has a weak pull-up, is open drain like, and requires an external 1.0KΩ pull-
up resistor.
12
MDC
I
Management Interface (MII) Clock Input
This clock pin is synchronous to the MDIO data pin.
13
RXD3 /
Ipu/O MII Mode:
MII Receive Data Output[3]⁽²⁾ /
PHYAD0
Config Mode: The pull-up/pull-down value is latched as PHYADDR[0] at the
de-assertion of reset. See “Strapping Options” section for details.
14
RXD2 /
Ipd/O MII Mode:
MII Receive Data Output[2]⁽²⁾ /
PHYAD1
Config Mode: The pull-up/pull-down value is latched as PHYADDR[1] at the
de-assertion of reset. See “Strapping Options” section for details.
15
RXD1 /
Ipd/O MII Mode:
MII Receive Data Output[1]⁽²⁾ /
PHYAD2
Config Mode: The pull-up/pull-down value is latched as PHYADDR[2] at the
de-assertion of reset. See “Strapping Options” section for details.
16
RXD0 /
Ipu/O MII Mode:
MII Receive Data Output[0]⁽²⁾ /
DUPLEX
Config Mode: The pull-up/pull-down value is latched as DUPLEX at the
de-assertion of reset. See “Strapping Options” section for details.
17
VDDIO
P
3.3V, 2.5V or 1.8V digital V_DD
18
RXDV /
Ipd/O MII Mode:
MII Receive Data Valid Output /
CONFIG2
Config Mode: The pull-up/pull-down value is latched as CONFIG2 at the
de-assertion of reset. See “Strapping Options” section for details.
19
RXC /
Ipd/O MII Mode:
MII Receive Clock Output
B-CAST_OFF
Config Mode: The pull-up/pull-down value is latched as B-CAST_OFF at the
de-assertion of reset. See “Strapping Options” section for details.
20
RXER /
Ipd/O MII Mode:
MII Receive Error Output /
ISO
Config Mode: The pull-up/pull-down value is latched as ISOLATE at the
de-assertion of reset. See “Strapping Options” section for details.
21
INTRP /
Ipu/Opu Interrupt Output: Programmable Interrupt Output
This pin has a weak pull-up, is open drain like, and requires an external 1.0KΩ pull-
up resistor.
July 2010
10
M9999-070910-1.0