KSZ8041TL_09 Datasheet, PDF (20/65 Pages) Micrel Semiconductor – 10Base-T/100Base-TX/100Base-FX Physical Layer Transceiver

Micrel, Inc.
Pin Number
43
Pin Name
LED1 /
SPEED
KSZ8041TL/FTL/MLL
Type⁽¹⁾
Ipu/O
Pin Function
LED Output: Programmable LED1 Output /
Config. Mode: Latched as SPEED (register 0h, bit 13) during power-up /
reset. See “Strapping Options” section for details.
The LED1 pin is programmable via register 1Eh bits [15:14], and is defined as
follows.
LED mode = [00]
Speed
Pin State
LED Definition
10BT
H
OFF
100BT
L
ON
LED mode = [01]
Activity
Pin State
No Activity
H
Activity
Toggle
LED Definition
OFF
Blinking
LED mode = [10] Reserved
LED mode = [11]
Reserved
44
NC
-
No connect
45
NC
-
No connect
46
NC
-
No connect
47
RST#
I
Chip Reset (active low)
48
NC
-
No connect
Notes:
1. P = Power supply.
Gnd = Ground.
I = Input.
O = Output.
I/O = Bi-directional.
Ipd = Input with internal pull-down (40K +/-30%).
Ipu = Input with internal pull-up (40K +/-30%).
Opu = Output with internal pull-up (40K +/-30%).
Ipu/O = Input with internal pull-up (40K +/-30%) during power-up/reset; output pin otherwise.
Ipd/O = Input with internal pull-down (40K +/-30%) during power-up/reset; output pin otherwise.
2. MII Rx Mode: The RXD[3..0] bits are synchronous with RXCLK. When RXDV is asserted, RXD[3..0] presents valid data to MAC through the MII.
RXD[3..0] is invalid when RXDV is de-asserted.
3. MII Tx Mode: The TXD[3..0] bits are synchronous with TXCLK. When TXEN is asserted, TXD[3..0] presents valid data from the MAC through
the MII. TXD[3..0] has no effect when TXEN is de-asserted.
December 2009
20
M9999-120909-1.2