KSZ8041TL_09 Datasheet, PDF (10/65 Pages) Micrel Semiconductor – 10Base-T/100Base-TX/100Base-FX Physical Layer Transceiver

Micrel, Inc.
KSZ8041TL/FTL/MLL
Pin Description- KSZ8041TL/FTL
Pin Number Pin Name
Type^{(1) Pin Function}
1
GND
Gnd
Ground
2
GND
Gnd
Ground
3
GND
Gnd
Ground
4
VDDA_1.8
P
1.8V analog V_DD
5
VDDA_1.8
P
1.8V analog V_DD
6
V1.8_OUT
P
1.8V output voltage from chip
7
VDDA_3.3
P
3.3V analog V_DD
8
VDDA_3.3
P
3.3V analog V_DD
9
RX-
I/O
Physical receive or transmit signal (- differential)
10
RX+
I/O
Physical receive or transmit signal (+ differential)
11
TX-
I/O
Physical transmit or receive signal (- differential)
12
TX+
I/O
Physical transmit or receive signal (+ differential)
13
GND
Gnd
Ground
14
XO
O
Crystal feedback
This pin is used only in MII mode when a 25MHz crystal is used.
This pin is a no connect if oscillator or external clock source is used, or if RMII
mode or SMII mode is selected.
15
XI /
I
Crystal / Oscillator / External Clock Input
REFCLK /
MII Mode:
25MHz +/-50ppm (crystal, oscillator, or external clock)
CLOCK
RMII Mode:
50MHz +/-50ppm (oscillator, or external clock only)
SMII Mode:
125MHz +/-100ppm (oscillator, or external clock only)
16
REXT
I/O
Set physical transmit output current
Connect a 6.49K: resistor in parallel with a 100pF capacitor to ground on this
pin. See KSZ8041TL-FTL reference schematics.
17
GND
Gnd
Ground
18
MDIO
I/O
Management Interface (MII) Data I/O
This pin requires an external 4.7K: pull-up resistor.
19
MDC
I
Management Interface (MII) Clock Input
This pin is synchronous to the MDIO data interface.
20
RXD3 /
Ipu/O
MII Mode:
Receive Data Output[3]⁽²⁾ /
PHYAD0
Config. Mode: The pull-up/pull-down value is latched as PHYADDR[0] during
power-up / reset. See “Strapping Options” section for details.
21
RXD2 /
Ipd/O
MII Mode:
Receive Data Output[2]⁽²⁾ /
PHYAD1
Config. Mode: The pull-up/pull-down value is latched as PHYADDR[1] during
power-up / reset. See “Strapping Options” section for details.
22
RXD1 /
Ipd/O
MII Mode:
Receive Data Output[1]⁽²⁾ /
RXD[1] /
RMII Mode:
Receive Data Output[1]⁽³⁾ /
PHYAD2
Config. Mode: The pull-up/pull-down value is latched as PHYADDR[2] during
power-up / reset. See “Strapping Options” section for details.
December 2009
10
M9999-120909-1.2