PL500-17 Datasheet, PDF (2/6 Pages) Micrel Semiconductor – Low Phase Noise VCXO (17MHz to 36MHz)

DIE PAD LAYOUT
32 mil
PL500-17
Low Phase Noise VCXO (17MHz to 36MHz)
(812,986)
DIE SPECIFICATIONS
1 XIN
8
XOUT
2 VDD
3 VCON
4 GND
DIE ID: C500xxxxxx
OE^ 7
VDD 6
CLK 5
Name
Size
Reverse side
Pad dimensions
Thickness
Value
39 x 32 mil
GND
80 micron x 80 micron
8 mil
Y ^(0,0)
X _{Note: ^ denotes internal pull up}
PACKAGE PIN AND DIE PAD ASSIGNMENT
Name
Pin#
Die Pad Position
SOP-8 SOT23-6 X (m) Y (m)
Type
Description
XIN
1
6
94.183 768.599
I Crystal input pin.
VDD
2
5
94.157 605.029
P
VDD power supply pin. Only one VDD pin is
necessary.
VCON
3
4
94.183 331.756
I
Frequency control voltage input pin.
GND
4
2
94.193 140.379 P Ground pin.
CLK
5
3
715.472 203.866 O Output clock pin.
VDD
6
-
715.307 455.726
P
VDD power supply pin. Only one VDD pin is
necessary.
OE*
7
Output Enable input pin. Disables the output
-
715.472 626.716
I
when low. Internal pull-up enables output by
default if pin is not connected to low.
XOUT
8
1
476.906 888.881
I Crystal output pin. Ref Clock input.
* OE (Output Enable) pin is not available in SOT23-6L package, the output will always be enabled by the build in pull-up resister.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel [phone] • fax [phone] • www.micrel.com Rev 6/15/10 Page 2