PL123E-05SC Datasheet, PDF (2/10 Pages) Micrel Semiconductor – Low Skew Zero Delay Buffer

(Preliminary )P L 1 2 3 E - 0 5
Low Skew Zero Delay Buffer
PIN DESCRIPTION
Name
REF^[1]
CLK2^[2]
CLK1^[2]
GND
CLK3^[2]
VDD
CLK4^[2]
CLKOUT ^{[2 ,3 ]}
Package Type
SOP-8L
1
2
3
4
5
6
7
8
Type
Description
I
Input reference frequency.
O
Buffered clock output.
O
Buffered clock output.
P
Ground connection.
O
Buffered clock output.
P
VDD connection.
O
Buffered clock output.
O
Buffered clock output. Internal feed back on this pin.
Notes: 1: Weak pull-down. 2: Weak pull-down on all outputs.
3. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the
skew between the reference and output.
INPUT / OUTPUT SKEW CONTROL
The PL123E-05 will achieve Zero Delay from input to output when all the outputs are loaded equally. Adjus t-
ments to the input/output delay can be made by adjusting the loading on the CLKOUT pin.
Please contact Micrel for more information.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel [phone] • fax [phone] • www.micrel.com Rev 12/13/11 Page 2