PL123-05NSC Datasheet, PDF (2/8 Pages) Micrel Semiconductor – Low Skew Fanout Buffer

PIN DESCRIPTIONS
Name
PL123-09N
SOP-16L
REF
1
CLK1
2
CLK2
3
VDD
4, 8, 13
GND
5, 9, 12
CLK3
6
CLK4
7
CLK5
10
CLK6
11
CLK7
14
CLK8
15
CLK9
16
PL123-05N
SOP-8L
1
2
3
6
4
5
7
8
-
-
-
-
PL123-05N/-09N
Low Skew Fanout Buffer
Type
I
O
O
P
P
O
O
O
O
O
O
O
Description
Input reference frequency.
Buffered clock output
Buffered clock output
VDD connection
GND connection
Buffered clock output
Buffered clock output
Buffered clock output
Buffered clock output
Buffered clock output
Buffered clock output
Buffered clock output
LAYOUT RECOMMENDATIONS
The following guidelines are to assist you with a pe rformance optimized PCB design:
Signal Integrity and Termination
Considerations
- Keep traces short!
- Trace = Inductor. With a capacitive load this equals
ringing!
- Long trace = Transmission Line. Without proper termi-
nation this will cause reflections ( looks like ringing ).
- Design long traces (> 1 inch) as “striplines” or
“microstrips” with defined impedance.
- Match trace at one side to avoid reflections bouncing
back and forth.
Decoupling and Power Supply
Considerations
- Place decoupling capacitors as close as possible
to the VDD pin(s) to limit noise from the power
supply
- Addition of a ferrite bead in series with VDD can
help prevent noise from other board sources
- Value of decoupling capacitor is frequency de-
pendant. Typical values to use are 0.1 F for de-
signs using frequencies < 50MHz and 0.01F for
designs using frequencies > 50MHz.
Typical CMOS termination
Place Series Resistor as close as possible to CMOS output
CMOS Output Buffer
( Typical buffer impedance 20 ohm)
50 ohm line
To CMOS Input
Connect a 33 ohm series resistor at each of the output clocks to
enhance the stability of the output signal
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel [phone] • fax [phone] • www.micrel.com Rev 03/15/12 Page 2