MIC2150 Datasheet, PDF (19/27 Pages) Micrel Semiconductor – 2-Phase Dual Output PWM Synchronous Buck Control IC

Micrel, Inc.
C3 = ^{2 × π × Fco × L × COUT} × ^VIN
RC1
V_RAMP
R3 =
1
2 × π × C3 × FP1
R2 = ^{R1× VREF}
V_OUT − V_REF
R1 =
1
− R3
2 × π × C3 × FZ2
Tantalum/Electrolytic Output Capacitor Designs
The closed loop bode plot response of the higher ESR
capacitor design looks something like the figure below.
Figure 13. Tantalum Output Capacitor Bode Plot
Due to the output capacitor ESR creating a zero within
the range of the desired crossover frequency (Fco), this
design only requires that one adds one zero and one
associated pole. The phase boost in this case occurs
between the zero (FZ) and the pole (FP) of the
compensator. Therefore, the zero gain crossover
frequency (Fco) will be between these two points. The
zero is created by RC1 and C1. The pole should be set
at ≤one half switching frequency to reduce noise
sensitivity. The plateau gain (gain between FZ and FP)
is set by RC1 and R1, Av_PLATEAU = RC1/R1, this should
be set to a modest gain of five-to-ten to improve
transient response. This compensation network is shown
in Figure 14.
MIC2150
Figure 14. Type II Compensation Network
Pole and Zero Positioning
Fo =
1
2 × π × L × C_OUT
To introduce a boost in phase at and beyond the
resonance of the output LC filter (Fo), FZ can be placed
at Fo.
FZ = Fo
Together with phase boost associated with the output
capacitor ESR zero, this will achieve up to 45 degrees
Phase margin. The noise suppression pole can be set to
one half switching frequency.
FP = ^FS
2
Calculating Network Values
Choose R1 <10k to reduce susceptibility to noise and
inaccuracies induced by the error amplifier bias current.
R1 = 1k
To set output voltage, set R2:
R2 = ^{R1× VREF}
V_OUT − V_REF
For a plateau gain of 5
RC1 = R1× 5
C1 =
1
2 × π × RC1× FZ
Assuming FZ<<FP, C2 can be approximated to:
C2 ≈
1
2 × π × RC1× FP
August 2009
19
M9999-082809-A
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