KSZ8852HLE Datasheet, PDF (171/190 Pages) Micrel Semiconductor – Two-Port 10/100 Mb/s Ethernet Switch with 8 or 16-Bit Host Interface

Micrel, Inc.
KSZ8852HLE
Table 23. "All Ports Dropped Packet" MIB Counter Format
Bit Default R/W Description
30−16
−
N/A Reserved
15−0 0x0000 RO Counter Value
Note: “All ports dropped packet” MIB Counters do not indicate overflow or validity; therefore, the application must keep track of overflow and valid
conditions.“
All ports dropped packet” MIB counters are read using indirect memory access. The address offsets for these counters
are shown in Table 27.
Table 24. "All Ports Dropped Packet" MIB Counters− Indirect Memory Offsets
Offset
Counter Name
Description
0x100 Port 1 TX Drop Packets TX packets dropped due to lack of resources
0x101 Port 2 TX Drop Packets TX packets dropped due to lack of resources
0x102 Port 3 TX Drop Packets TX packets dropped due to lack of resources
0x103 Port 1 RX Drop Packets RX packets dropped due to lack of resources
0x104 Port 2 RX Drop Packets RX packets dropped due to lack of resources
0x105 Port 3 RX Drop Packets RX packets dropped due to lack of resources
MIB Counter Examples:
9. MIB Counter Read (read Port 1 “Rx64Octets” counter at indirect address offset 0x0E)
Write to Reg. IACR with 0x1c0e (set indirect address and trigger a read MIB counters operation)
Then:
Read Reg. IADR5 (MIB counter value [31:16]) // If bit [31] = 1, there was a counter overflow, // If bit [30] = 0,
restart (re−read) from this register
Read Reg. IADR4 (MIB counter value 15:0)
10. MIB Counter Read (read Port 2 “Rx64Octets” counter at indirect address offset 0x2E)
Write to Reg. IACR with 0x1c2e (set indirect address and trigger a read MIB counters operation)
Then:
Read Reg. IADR5 (MIB counter value [31:16]) // If bit [31] = 1, there was a counter overflow, // If bit [30] = 0,
restart (re−read) from this register
Read Reg. IADR4 (MIB counter value [15:0])
11. MIB Counter Read (read “Port 1 TX Drop Packets” counter at indirect address offset 0x100)
Write to Reg. IACR with 0x1D00 (set indirect address and trigger a read MIB counters operation)
Then:
Read Reg. IADR4 (MIB counter value [15:0])
Additional MIB Information
Per port MIB counters are designed as “read clear”. That is, these counters will be cleared after they are read.
All ports dropped packet MIB counters are not cleared after they are accessed. The application needs to keep track of
overflow and valid conditions on these counters.
August 31, 2015
171
Revision 1.1