KSZ8852HLE Datasheet, PDF (139/190 Pages) Micrel Semiconductor – Two-Port 10/100 Mb/s Ethernet Switch with 8 or 16-Bit Host Interface

Micrel, Inc.
KSZ8852HLE
Port 2 EEE and Link Partner Advertisement Register (0x0EC - 0x0ED): P2EEEA (Continued)
This register contains the Port 2 EEE advertisement and link partner advertisement information.
Bit Default R/W Description
1000BASE-KX EEE
12
0
RO 1 = Link Partner EEE is supported for 1000BASE-KX.
0 = Link Partner EEE is not supported for 1000BASE-KX.
10GBASE-T EEE
11
0
RO 1 = Link Partner EEE is supported for 10GBASE-T.
0 = Link Partner EEE is not supported for 10GBASE-T.
1000BASE-T EEE
10
0
RO 1 = Link Partner EEE is supported for 1000BASE-T.
0 = Link Partner EEE is not supported for 1000BASE-T.
100BASE-TX EEE
9
0
RO 1 = Link Partner EEE is supported for 100BASE-TX.
0 = Link Partner EEE is not supported for 100BASE-TX.
8–7
00
RO Reserved
10GBASE-KR EEE
6
0
RO 1 = Port 2 EEE is supported for 10GBASE-KR.
0 = Port 2 EEE is not supported for 10GBASE-KR.
10GBASE-KX4 EEE
5
0
RO 1 = Port 2 EEE is supported for 10GBASE--KX4.
0 = Port 2 EEE is not supported for 10GBASE-KX4.
1000BASE-KX EEE
4
0
RO 1 = Port 2 EEE is supported for 1000BASE-KX.
0 = Port 2 EEE is not supported for 1000BASE-KX.
10GBASE-T EEE
3
0
RO 1 = Port 2 EEE is supported for 10GBASE-T.
0 = Port 2 EEE is not supported for 10GBASE-T.
1000BASE-T EEE
2
0
RO 1 = Port 2 EEE is supported for 1000BASE-T.
0 = Port 2 EEE is not supported for 1000BASE-T.
100BASE-TX EEE
1 = Port 2 EEE is supported for 100BASE-TX.
1
1
RW
0 = Port 2 EEE is not supported for 100BASE-TX.
To disable EEE capability, clear the Port 2 Next Page Enable bit in the PCSEEEC register (0x0F3).
0
0
RO Reserved
Port 2 EEE Wake Error Count Register (0x0EE - 0x0EF): P2EEEWEC
This register contains the Port 2 EEE wake error count information.
Bit
15−0
Default Value
0x0000
R/W Description
Port 2 EEE Wake Error Count
This counter is incremented by each transition of lpi_wake_timer_done from FALSE to TRUE. It
RW means the wake-up time is longer than 20.5µs.
The value will be held at all ones in the case of overflow and will be cleared to zero after this
register is read.
August 31, 2015
139
Revision 1.1