KSZ8852HLE Datasheet, PDF (164/190 Pages) Micrel Semiconductor – Two-Port 10/100 Mb/s Ethernet Switch with 8 or 16-Bit Host Interface

Micrel, Inc.
KSZ8852HLE
Interrupt Status Register (0x192 - 0x193): ISR (Continued)
Bit Default Value
R/W
Description
TXPSIS Transmit Process Stopped Interrupt Status
9
0
RO (W1C) When this bit is set, it indicates that the transmit process has stopped.
This edge-triggered interrupt status is cleared by writing a “1” to this bit.
RXPSIS Receive Process Stopped Interrupt Status
8
0
RO (W1C) When this bit is set, it indicates that the receive process has stopped.
This edge-triggered interrupt status is cleared by writing a “1” to this bit.
7
0
RO
Reserved
TXSAIS Transmit Space Available Interrupt Status
6
0
RO (W1C)
When this bit is set, it indicates that transmit memory space available status has occurred.
5
0
RXWFDIS Receive Wake-Up Frame Detect Interrupt Status
RO
When this bit is set, it indicates that a Wake-Up frame has been received. Write “1000” to
PMCTRL[5:2] to clear this bit.
4
0
RXMPDIS Receive Magic Packet Detect Interrupt Status
RO
When this bit is set, it indicates that a Magic Packet has been received. Write “0100” to
PMCTRL[5:2] to clear this bit.
3
0
LDIS Linkup Detect Interrupt Status
RO
When this bit is set, it indicates that wake-up from linkup detect status has occurred. Write
“0010” to PMCTRL[5:2] to clear this bit.
2
0
EDIS Energy Detect Interrupt Status
When this bit is set and bit [2] = “1”, bit [0] = “0” in the IER register, it indicates that wake−up
RO
from energy detect status has occurred. When this bit is set and bit [2, 0] = “1” in the IER
register, it indicates that wake−up from energy detect status has occurred.
Write “0001” to PMCTRL[5:2] to clear this bit.
1−0
00
RO
Reserved
0x194 - 0x19B: Reserved
August 31, 2015
164
Revision 1.1