MIC2085 Datasheet, PDF (16/29 Pages) Micrel Semiconductor – Single Channel Hot Swap Controllers

Micrel, Inc.
MIC2085/2086
connected to CPOR sets the interval, t_POR, and t_POR is
equivalent to the start-up delay, t_START (see Equation 1).
A capacitor connected to CFILTER is used to set the
timer which activates the circuit breaker during
overcurrent conditions. When the voltage across the
sense resistor exceeds the slow trip current limit
threshold of 48mV, the overcurrent timer begins to
charge for a period, t_OCSLOW, determined by CFILTER. If
no capacitor is used at CFILTER, then t_OCSLOW defaults
to 5µs. If t_OCSLOW elapses, then the circuit breaker is
activated and the GATE output is immediately pulled to
ground. The following equation is used to determine the
overcurrent timer period, t_OCSLOW.
( ) t _OCSLOW
=
C_FILTER
×
V_TH
I_TIMER
≅ 0.062 × C_FILTER µF
(7)
where V_TH, the CFILTER timer threshold, is 1.24V and
I_TIMER, the overcurrent timer current, is 20µA. Tables 2
and 3 provide a quick reference for several timer
calculations using select standard value capacitors.
C_POR
0.01µF
t_POR = t_START
6ms
0.02µF
12ms
0.033µF
0.05µF
18.5ms
30ms
0.1µF
60ms
0.33µF
200ms
Table 2. Selected Power-On Reset and
Start-Up Delays
C_FILTER
1800pF
4700pF
t_OCSLOW
100µs
290µs
8200pF
500µs
0.01µF
0.02µF
620µs
1.2ms
0.033µF
2.0ms
0.05µF
0.1µF
0.33µF
3.0ms
6.2ms
20.7ms
Table 3. Selected Overcurrent Timer Delays
Application Information
Output Undervoltage Detection
For output undervoltage detection, the first consideration
is to establish the output voltage level that indicates
“power is good.” For this example, the output value for
which a 12V supply will signal “good” is 11V. Next,
consider the tolerances of the input supply and FB
threshold (VFB). For this example, the 12V supply varies
±5%, thus the resulting output voltage may be as low as
11.4V and as high as 12.6V. Additionally, the FB
threshold has ±50mV tolerance and may be as low
as1.19V and as high as 1.29V. Thus, to determine the
values of the resistive divider network (R5 and R6) at the
FB pin, shown in Figure 5, use the following iterative
design procedure.
1) Choose R6 so as to limit the current through the
divider to approximately 100µA or less.
R6 ≥ ^VFB(MAX) ≥ ^1.29V ≥ 12.9kΩ
100µΑ 100µΑ
R6 is chosen as 13.3kΩ ± 1%
2) Next, determine R5 using the output “good”
voltage of 11V and the following equation:
( ) _VOUT(Good)
=
V_FB
⎡
⎢⎣
R5 + R6
R6
⎤
⎥⎦
(8)
Using some basic algebra and simplifying Equation 8 to
isolate R5, yields:
R5
=
R6_{⎢⎢⎣⎡⎜⎜⎝⎛}
V_OUT(Good)
V_FB(MAX)
⎟⎞
⎟⎠
−
⎤
1⎥
⎥⎦
(8.1)
where V_FB(MAX) = 1.29V, V_OUT(Good) = 11V, and R6
is13.3kΩ. Substituting these values into Equation 8.1
now yields R5 = 100.11kΩ. A standard 100kΩ ± 1% is
selected. Now, consider the 11.4V minimum output
voltage, the lower tolerance for R6 and higher tolerance
for R5, 13.17kΩ and101kΩ, respectively. With only
11.4V available, the voltage sensed at the FB pin
exceeds V_FB(MAX), thus the /POR and PWRGD
(MIC2086) signals will transition from LOW to HIGH,
indicating “power is good” given the worse case
tolerances of this example.
Input Overvoltage Protection
The external CRWBR circuit shown in Figure 5 consists
of capacitor C4, resistor R7, NPN transistor Q2, and
SCR Q3.The capacitor establishes a time duration for an
overvoltage condition to last before the circuit breaker
trips. The CRWBR timer duration is approximated by the
following equation:
t _OVCR
≅
(C4 × V_CR )
I_CR
≅
0.01× C4(µF)
(9)
where V_CR, the CRWBR pin threshold, is 0.47V and I_CR,
the CRWBR pin current, is 45µA during the timer period
(see the CRWBR timer pin description for further
description). A similar design approach as the previous
undervoltage detection example is recommended for the
May 2006
16
M9999-050406
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