MIC2155_0911 Datasheet, PDF (15/35 Pages) Micrel Semiconductor – Two-Phase, Single-Output, PWM Synchronous Buck Control IC

Micrel, Inc.
Oscillator and Frequency Synchronization
The internal oscillator free runs at a fixed frequency and
requires no external components. The oscillator
generates two clock signals that are 180° out of phase
with each other. This forces each channel of the
controller to switch 180° out of phase, which reduces
input and output ripple current.
The internal oscillator generates a clock signal and ramp
signal. The clock signal terminates the switching cycle
for each channel. The ramp voltage for Channel 1 is
compared with the output of the error amplifier and
regulates the output voltage. The ramp signal for
Channel 2 is compared with the Channel 2 error
amplifier output and forces the output current of Channel
2 to match Channel 1.
RMP1
SYNC
CLK1
RMP2
CLK2
2 Phase
Oscillator
Figure 8. Oscillator and Sync Diagram
The SYNC input (pin 15) allows the MIC2155/6 to
synchronize to an external clock signal. When
synchronized, each channel switches at half of the
synchronization frequency. Limitations on the
synchronization frequency and signal amplitude are
listed in the electrical characteristics section of the spec.
When not used, the sync pin should be left open (no
connect).
MOSFET Gate-Drive Circuitry
The high-side drive circuit is designed to switch an N-
channel MOSFET. Figure 9 shows a diagram of the gate
drive and bootstrap circuit. D2 and C_BST comprise the
bootstrap circuit, which is used to supply drive voltage to
the high-side FET. Bootstrap capacitor C_BST is charged
through diode D2 while the low-side MOSFET is on and
the voltage on the SW pin is approximately 0V. When
the high-side MOSFET driver is turned on, energy from
C_BST is used to charge the MOSFET gate, turning on the
FET. As the MOSFET turns on, the voltage on the SW
pin increases to approximately V_IN. Diode D2 is reversed
biased and C_BST is pulled high while continuing to keep
the high-side MOSFET on. The high-side drive voltage,
which is derived from V_DD, is approximately 4.5V due the
voltage drop across D2. When operating at 4.5V_IN,
without connecting V_DD to V_IN, the gate drive voltage to
the high-side FET could be as low as 3.2V. MOSFETs
MIC2155/2156
with an appropriate V_GS threshold should be used in this
situation.
The voltage on the bootstrap capacitor drops each time
it delivers charge to turn on the MOSFET. The voltage
drop depends on the gate charge required by the
MOSFET. Most MOSFET specifications specify gate
charge vs. V_GS voltage. Based on this information and a
recommended ΔVHB of less than 0.1V, the minimum
value of bootstrap capacitance is calculated as:
C_BST
≥
Q_GATE
ΔV_BST
Where:
Q_GATE = Total Gate Charge a V_BST
ΔV_BST = Voltage drop at the BST pin
A minimum value of 0.1µF is required for each of the
bootstrap capacitors, regardless of the MOSFETs being
driven. Larger or paralleled MOSFETs may require
larger capacitance values for proper operation.
Placement is critical. The bypass capacitor (C_BST) for the
BST supply pins must be located close between the BST
and SW1 pins. The etch connections should be short,
wide and direct. The use of a ground plane to minimize
connection impedance is recommended. Refer to the
section on layout and component placement for more
information.
A delay between the switching of the two MOSFETs is
necessary to prevent both MOSFETs from being on at
the same time and shorting V_IN to ground. An adaptive
gate drive in the controller monitors the switch node
(SW1) and low-side driver (LSD1) to minimize dead time
while preventing both MOSFETs from being on at the
same time. This enables the use of a broad range of
MOSFETS without requiring excessive deadtime.
November 2009
15
M9999-111209-B